Detailing Influence of Contact Condition and Island Edge on Dual-Configuration Kelvin Pseudo-MOSFET Method Reviewed

MORI, Daigo, NAKATA, Iori, MATSUDA, Masayoshi, SATO, Shingo

IEEE Transactions on Electron Devices   vol. 68, No. 6, pp.2906-2911   2021.4

Theoretical analysis of the impacts of light illumination on the transient current of sputter-deposited non-doped ZnO films Reviewed

OMURA, Yasuhisa, SATO,Shingo

AIP Advances   11, 015030   2021.1

Impact of light and ambient gas on the resistance of sputter-deposited non-doped ZnO films

Yasuhisa Omura, Shingo Sato

Proceedings of SPIE - The International Society for Optical Engineering   11281   2020

Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFET Reviewed

S. Sato, G. Ghibaudo, L. Benea, I. Ionica, Y. Omura, S. Cristloveanu

Solid State Electronics   Vol. 159, Sep. 2019, pp. 197-203   2019.9

Measuring Impact of Light on the Resistance of Non-Doped ZnO Films Reviewed

TAKAHASHI, Naoto, SATO,Shingo, OMURA, Yasuhisa, SAITOH, Tadashi

ECS Journal of Solid State Science and Technology   volume 8, issue 1, pp. 57-61, 2019   2019.2

Analysis of miller capacitance in si tunnel field-effect transistors and potential for low-voltage/low-energy applications

Yuyang Jiang, Shingo Sato, Yasuhisa Omura, Abhijit Mallik

International Journal on Engineering Applications   7 ( 3 )   88 - 96   2019

Aspects and Reduction of Miller Capacitance of Lateral Tunnel FETs

Yuyang Jiang, Shingo Sato, Yasuhisa Omura, Abhijit Mallik

IMFEDK 2018 - 2018 International Meeting for Future of Electron Devices, Kansai   2018.12

Study on the Impacts of Hole Injection and Inclusion of Sub-oxide and Metallic Si Atoms on Repeatable Resistance Switching of Sputter-Deposited Silicon Oxide Films Reviewed

Y. Omura, R. Yamaguchi, S. Sato

IEEE Transactions on Device and Materials Reliability   Volume: 18, Issue:4, pp.561-567   2018.12

Detailed analysis of frequency-dependent impedance in pseudo-MOSFET on thin SOI film

S. Sato, Y. Omura, G. Ghibaudo, L. Benea, S. Cristoloveanu

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018   2018-   1 - 4   2018.5

Possible Models of Electron-Energy Transfer in Resistance Switching by Sputter-Deposited Silicon Oxide Films: Potential of Extremely Low-Energy Switching Reviewed

Y. Omura, T. Akano, S. Sato

ECS Journal of Solid State Science and Technology   volume 7, issue 3, Q21-Q25   2018.2

Novel Addressable Test Structure for Detecting Soft Failure of Resistive Elements when Developing Manufacturing Procedures Reviewed

S. Sato, Y. Omura

IEEE Transactions on Semiconductor Manufacturing   Vol. 31, Issue. 1, pp.124-129   2018

Revisiting the Role of Trap-Assisted-Tunneling Process on Current-Voltage Characteristics in Tunnel Field-Effect Transistors Reviewed

Y. Omura, Y. Mori, S. Sato, A. Mallik

Journal of Applied Physics   vol. 123, pp. 161549-1-161549-6   2017.12

On the Definition of Threshold Voltage for Tunnel FETs Reviewed

Y. Mori, S. Sato, Y. Omura, A. Chattopadhyay, A. Mallik

Superlattices and Microstructures   vol. 107, pp. 17-27   2017.4

Roles of chemical stoichiometry and hot electrons in realizing the stable resistive transition of sputter-deposited silicon oxide films Reviewed

R. Yamaguchi, S. Sato, Y. Omura

Japanese Journal of Applied Physics   vol. 56, No. 4, pp. 041301-1-041301-6 ( 4 )   41301 - 41301   2017.3

Impact of native oxide growth on the capacitance-voltage characteristic of pseudo-MOS structure

Isao Yarita, Shingo Sato, Yasuhisa Omura

ECS Transactions   77 ( 11 )   1887 - 1892   2017

Sensitivity of resistive transition of sputter-deposited TiO2 films to electrode material

N. Kawashima, S. Sato, Y. Omura

IMFEDK 2016 - 2016 International Meeting for Future of Electron Devices, Kansai   2016.7

Proposal of Physics-Based Equivalent Circuit of Pseudo-MOS Capacitor Structure for Impedance Spectroscopy

Isao Yarita, Shingo Sato, Yasuhisa Omura

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY   4 ( 4 )   169 - 173   2016.7

A Possible Threshold Voltage Definition of Lateral Tunnel FET Reviewed

Yoshiaki Mori, Shingo Sato, Yasuhisa Omura, Abhijit Mallik

2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW)   188 - 189   2016

Capacitance Analysis of Pseudo-MOSFET Using Cole-Cole Plots Reviewed

Isao Yarita, Shingo Sato, Yasuhisa Omura

2016 IEEE INTERNATIONAL MEETING FOR FUTURE OF ELECTRON DEVICES, KANSAI (IMFEDK)   36 - 37   2016

Possible theoretical models for carrier diffusion coefficient of one-dimensional Si wire devices

Shingo Sato, Yasuhisa Omura

JAPANESE JOURNAL OF APPLIED PHYSICS   54 ( 5 )   2015.5

Compact model for nano-wire tunnel field-effect transistor

Shingo Sato, Yasuhisa Omura, Abhijit Mallik

ECS Transactions   66 ( 5 )   171 - 177   2015

Physics-based Model for the Conductive Filament at the Low Resistance State of Thin SiO2 Films Reviewed

Rintaro Yamaguchi, Shingo Sato, Yasuhisa Omura

2015 SILICON NANOELECTRONICS WORKSHOP (SNW)   2015

Circuit Architecture and Measurement Technique to Reduce the Leakage Current Stemming from Peripheral Circuits with an Array Structure in Examining the Resistive Element Reviewed

Shingo Sato, Takaki Ito, Yasuhisa Omura

PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS 2015)   14 - 17   2015

Analytically modeling the asymmetric double gate tunnel FET

Hongfei Lv, Shingo Sato, Yasuhisa Omura, Abhijit Mallik

ECS Transactions   66 ( 5 )   193 - 200   2015

Two-Dimensional Model for Asymmetric Double-Gate Tunnel FET Considering the Source-Channel Junction Depletion Region Reviewed

Hongfei Lv, Shingo Sato, Yasuhisa Omura, Abhijit Mallik

2015 IEEE INTERNATIONAL MEETING FOR FUTURE OF ELECTRON DEVICES, KANSAI (IMFEDK)   2015

Analysis of Soft Failures in Low-Resistance Interconnect Vias Using Doubly Nesting Arrays

Hiroki Shinkawata, Shingo Sato, Atsushi Tsuda, Tomoaki Yoshizawa, Takio Ohno

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING   27 ( 2 )   178 - 183   2014.5

Spectroscopic Electrical Characterization of Post-Resistive-Transition SiO2 Films Reviewed

R. Yamaguchi, S. Sato, Y. Omura, K. Nakamura

2014 IEEE INTERNATIONAL MEETING FOR FUTURE OF ELECTRON DEVICES, KANSAI (IMFEDK)   2014

Characterization of Noise Behavior of Ultrathin Inversion-Channel and Buried-Channel SOI MOSFETs in the Subthreshold Bias Range Reviewed

T. Ito, S. Sato, Y. Omura

2014 IEEE INTERNATIONAL MEETING FOR FUTURE OF ELECTRON DEVICES, KANSAI (IMFEDK)   2014

Theoretical Modeling for Carrier Diffusion Coefficient of One-Dimensional Si Wires around Room Temperature Reviewed

Yasuhisa Omura, Shingo Sato

2014 IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC)   2014

Characterization and Modeling of Resistive-Transition Phenomena and Electronic Structure of Sputter-Deposition SiO2 Films Reviewed

R. Yamaguchi, S. Sato, Y. Omura, K. Nakamura

2014 11TH INTERNATIONAL WORKSHOP ON LOW TEMPERATURE ELECTRONICS (WOLTE)   69 - 72   2014

Low-Temperature Behaviors of Phonon-Limited Electron Mobility of Sub-10-nm-Thick Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels

Yasuhisa Omura, Tsuyoshi Yamamura, Shingo Sato

JAPANESE JOURNAL OF APPLIED PHYSICS   48 ( 7 )   2009.7

Impact of band alignment on line electron density and channel capacitance of rectangular n-channel gate-all-around wire field-effect transistor

Shingo Sato, Yasuhisa Omura

JAPANESE JOURNAL OF APPLIED PHYSICS   47 ( 3 )   1706 - 1712   2008.3

Phonon-limited electron mobility behavior and inherent mobility reduction mechanism of ultrathin silicon-on-insulator layer with (111) surface and ultrathin germanium-on-insulator layer with (001) surface

Tsuyoshi Yamamura, Shingo Sato, Yasuhisa Omura

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   46 ( 12 )   7654 - 7661   2007.12

Empirical models of phonon-limited electron mobility for ultrathin-body single-gate and double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors with (001) or (111) Si surface channel

Tsuyoshi Yamamura, Shingo Sato, Yasuhisa Omura

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   46 ( 6A )   3463 - 3470   2007.6

Features of phonon-limited electron mobility behavior of double-gate field-effect transistor with (111) Si surface channel

Tsuyoshi Yamamura, Shingo Sato, Yasuhisa Omura

APPLIED PHYSICS LETTERS   90 ( 10 )   2007.3

Low-Temperature Behavior Simulations of Phonon-Limited Electron Mobility for Sub-10-nm-Thick SOI MOSFET with (111) or (001) Si Surface Channel Reviewed

Tsuyoshi Yamamura, Shingo Sato, Yasuhisa Omura

2007 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS   57 - 58   2007

Impact of phonon-limited mobility superiority in double-gate or FinFET with a (111) silicon and (001) germanium surface channel on device scaling

T. Yamamura, S. Sato, Y. Omura

ECS Transactions   6 ( 4 )   369 - 374   2007

Origin of transient gate current observed in pseudo-MOS transistor

Shingo Sato, Nguyen Quang Tuan, Sorin Cristoloveanu, Yasuhisa Omura

ECS Transactions   6 ( 4 )   95 - 100   2007

Quantum-mechanical suppression and enhancement of SCEs in ultrathin SOI MOSFETs

Y Omura, H Konishi, S Sato

IEEE TRANSACTIONS ON ELECTRON DEVICES   53 ( 4 )   677 - 684   2006.4

Physics-based determination of carrier effective mass assumed in density gradient model

S Sato, Y Omura

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   45 ( 2A )   689 - 693   2006.2

Possible influence of the Schottky contacts on the characteristics of ultrathin SOI pseudo-MOS transistors

S Sato, K Komiya, N Bresson, Y Omura, S Cristoloveanu

IEEE TRANSACTIONS ON ELECTRON DEVICES   52 ( 8 )   1807 - 1814   2005.8

Detailed investigation of geometrical factor for Pseudo-MOS transistor technique Reviewed

K Komiya, N Bresson, S Sato, S Cristoloveanu, Y Omura

IEEE TRANSACTIONS ON ELECTRON DEVICES   52 ( 3 )   406 - 412   2005.3

Impact of the schottky contacts on characterization of ultra-thin SOI pseudo-MOS transistors

S. Sato, K. Komiya, N. Bresson, Y. Omura, S. Cristoloveanu

Proceedings - Electrochemical Society   PV 2005-03   249 - 254   2005

Impact of high-k plug on self-heating effects of SOI MOSFETs

K Komiya, T Kawamoto, S Sato, Y Omura

IEEE TRANSACTIONS ON ELECTRON DEVICES   51 ( 12 )   2249 - 2251   2004.12

Engineering S/D diffusion for sub-100-nm channel SOI MOSFETs Reviewed

A Kawamoto, S Sato, Y Omura

IEEE TRANSACTIONS ON ELECTRON DEVICES   51 ( 6 )   907 - 913   2004.6

Engineering Source and Drain Diffusion for Sub-100-nm Channel Silicon-on-Insulator MOSFETs

A. Kawamoto, S. Sato, Y. Omura

IEEE Trans. Electron Devices   vol. 51, pp. 907-913   2004

Detailed investigation of geometrical factor for pseudo-MOS transistor technique

K Komiya, N Bresson, S Sato, S Cristoloveanu, Y Omura

2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS   vol. 52, pp. 406-412   75 - 76   2004

Measuring impact of light on resistance of non-doped ZnO films

N. Takahashi, S. Sato, Y. Omura, T. Saitoh

Advanced NanoMaterials Conf., <Nanosmat Society> (Aveiro, Portugal, 2018)  2018 

Definite Influence of Substrate-contact Condition on SOI Substrate Impedance Parameters

I. Yarita, S. Sato, Y. Omura

Proc. IEEE S3S Conference 2017 (Oct., San Francisco)  2017.10 

Important Roles of Hole Injection and Inclusion of Sub-oxide and Metallic Si Atoms on Resistive Transition of Sputter-Deposited Silicon Oxide Films

Y. Omura, R. Yamaguchi, S. Sato

Proceedings of Nano S & T 2017  2017.10 

Theoretical Models for Low-Frequency Noise Behaviors of Buried-Channel MOSFETs

Y. Omura, S. Sato

Proc. IEEE S3S Conference 2017 (Oct., San Francisco)  2017.10 

Physical Mechanisms of Short-Channel Effects of Lateral Double-Gate Tunnel FET

Y. Mori, S. Sato, Y. Omura, A. Mallik

Proceedings of Nano S & T 2017  2017.10 

<Invited>Theoretical Models for Electron Diffusion Coefficient of One-Dimensional Si Wire Devices: impacts of conduction band non-parabolicity-

Y. Omura, S. Sato

Proceedings of Nano S & T 2017  2017.10 

Pseudo-MOS構造のC-V特性に及ぼす自然酸化膜の影響

鑓田勲, 佐藤伸吾, 大村泰久

第78回応用物理学会秋季学術講演会 講演予稿集（2017 博多国際会議場）  2017.9 

Impact of Crystal Orientation and Conduction Band Non-parabolicity on Diffusion Constant of Nano-scale Si Rectangular Wires - theoretical estimation

Y. Omura, S. Sato

12th Nanosmat Conf. (Paris, Sept., 2017)  2017.9 

縦型tunnel FETにおけるTAT 電流の効果に関する考察

森義暁, 佐藤伸吾, 大村泰久, Abhijit Mallik

第78回応用物理学会秋季学術講演会 講演予稿集（2017 博多国際会議場）  2017.9 

Physical Mechanisms of Short-Channel Effects of Lateral Double-Gate Tunnel FET

Y. Mori, S. Sato, Y. Omura, A. Mallik

abstract of IMFEDK 2017  2017.6 

Impact of native oxide on the capacitance-voltage characteristic for pseudo-MOS structure

I. Yarita, S. Sato, Y. Omura

The 231st Electrochemical Society Meeting  2017.3 

<Invited>Recent Progress of Pseudo-MOS Method Used for Evaluating Electrical Properties of the SOI Wafer

S. Sato, I. Yarita, Y. Omura

Proc. 4th int. Symp. Semicond. Mat. And Devices  2017.3 

横型Tunnel FET の閾値電圧と短チャネル効果の考察

森義暁, 佐藤伸吾, 大村泰久, Abhijit Mallik

第64回応用物理学会春季学術講演会 講演予稿集 (2017 パシフィコ横浜), 予稿  2017.3 

縦型TFETの性能に及ぼすバラメ-タの影響の評価

蒋煜煬, 森義暁, 佐藤伸吾, 大村泰久, Abhijit Mallik

第78回応用物理学会秋季学術講演会 講演予稿集（2017 博多国際会議場）  2017.3 

スパッタ堆積 ZnO 薄膜の大気暴露による電気的特性の経時変化の評価

髙橋直人, 張捷生, 齊藤正, 佐藤伸吾, 大村泰久

第64回応用物理学会春季学術講演会 講演予稿集 (2017 パシフィコ横浜), 予稿  2017.3 

スパッタ堆積SiO2膜の抵抗変化現象の特徴

赤野拓哉, 山口凜太郎, 佐藤伸吾, 大村泰久

第63回応用物理学会春季学術講演会 講演予稿集 (2016 東京工業大学 大岡山キャンパス), 予稿  2016 

Sensitivity of Resistive Transition of Sputter-Deposited TiO2 Films to Electrode Material

N. Kawashima, S. Sato, Y. Omura

Tech. Dig. of IEEE IMFEDK 2016  2016 

スパッタ堆積TiO2膜の抵抗変化現象に関する考察

川嶋望, 佐藤伸吾, 大村泰久

第63回応用物理学会春季学術講演会 講演予稿集 (2016 東京工業大学 大岡山キャンパス), 予稿  2016 

A Possible Threshold Voltage Definition of Lateral Tunnel FET,

Y. Mori, S. Sato, Y. Omura, A. mallik

Abstracts of 2016 IEEE Silicon Nanoelectronics WS  2016 

Capacitance Analysis of Pseudo-MOSFET Using Cole-Cole Plots

I. Yarita, S. Sato, Y. Omura

Tech. Digest of IEEE IMFEDK 2016  2016 

Proposal of a New Array Structure to Enable the Detection of Soft Failure and the Aging Test with Overcurrent of Resistive Element

S. Sato, Y. Omura

Proceedings of 29th IEEE International Conference on Microelectronic Test Structures  2016 

Stable Unipolar and Bipolar Resistive Transitions of Sputter-Deposited SiO2 Films

R. Yamaguchi, T. Akano, S. Sato, Y. Omura

Abstracts of 2016 IEEE Silicon Nanoelectronics WS  2016 

スパッタ堆積ZnO 薄膜のキャリア生成とO1s スペクトルとの関係

張捷生, 佐藤伸吾, 斉藤正, 大村泰久

第63回応用物理学会春季学術講演会 講演予稿集 (2016 東京工業大学 大岡山キャンパス), 予稿  2016 

Pseudo-MOSを使った SOI基板のac解析手法の検討

鑓田勲, 佐藤伸吾, 大村泰久

第63回応用物理学会春季学術講演会 講演予稿集 (2016 東京工業大学 大岡山キャンパス) , 予稿  2016 

横型Tunnel FET の閾値状態の定義についての考察

森義暁, 佐藤伸吾, 大村泰久

第63回応用物理学会春季学術講演会 講演予稿集 (2016 東京工業大学 大岡山キャンパス), 予稿  2016 

スパッタ堆積SiO2膜の抵抗変化現象に対するキャリアエネルギーの影響

山口凜太郎, 佐藤伸吾, 大村泰久

第63回応用物理学会春季学術講演会 講演予稿集 (2016 東京工業大学 大岡山キャンパス), 予稿  2016 

Two-Dimensional Model for Asymmetric Double-Gate Tunnel FET Considering the Source-Channel Junction Depletion Region

H. Lv, S. Sato, Y. Omura, A. Mallik

IEEE IMFEDK2015  2015 

Development of a Compacted Doubly Nesting Array in Narrow Scribe Line Aimed at Detecting Soft Failures of Interconnect Via

H. Shinkawata, N. Tsuboi, A. Tsuda, S. Sato, Y. Yamaguchi

28th IEEE International Conference on Microelectronic Test Structures  2015 

Physics-based Model for the Conductive Filament at the Low Resistance State of Thin SiO2 Films

R. Yamaguchi, S. Sato, Y. Omura

JSAP Si Nanoelectronics WS  2015 

An Analytical Modeling for Asymmetric Double-Gate Tunnel FET Operation

H. Lv, S. Sato, Y. Omura, A. Mallik

227th ECS Meeting, Int. Symp. on Advanced CMOS-Compatible Semiconductor Devices 17th  2015 

Two-Dimensional Potential Model for Asymmetric Double-Gate Tunnel FET Considering the Source-Channel Junction Depletion Region

H. Lv, S. Sato, Y. Omura, A. Mallik

Tech. Dig., IEEE IMFEDK  2015 

Compact Modeling for Nano-Wire Tunnel Field Effect Transistor

S. Sato, Y. Omura, A. Mallik

227th ECS Meeting, Int. Symp. on Advanced CMOS-Compatible Semiconductor Devices 17th  2015 

半断線ビア抵抗を検出するためのスクライブライン搭載アレイTEG技術の開発

新川田裕樹, 坪井信生, 津田淳史, 佐藤伸吾, 山口泰男

電子情報通信学会、信学技報  2015 

Circuit Architecture and Measurement Technique to Reduce the Leakage Current Stemming from Peripheral Circuits with an Array Structure in Examining the Resistive Element

S. Sato, T. Ito, Y. Omura

Proceedings of the 2015 IEEE International Conference on Microelectronic Test Structures  2015 

Theoretical Modeling for Carrier Diffusion Coefficient in One-Dimensional Si Wires around Room Temperature

Y. Omura, S. Sato

Proc. of IEEE Nanoelectron. Conf.  2014 

Proposal of Simple Channel-Length-Dependent Current Model for Subthreshold Region of Nano-wire Tunnel FET

S. Sato, Y. Omura, A. Mallik

Tech. Dig., Compact Modeling,  2014 

Characterization of Noise Behavior of Ultrathin Inversion-Channel and Buried-Channel SOI MOSFETs in the Subthreshold Bias Range,

T. Ito, S. Sato, Y. Omura

Tech. Dig., IEEE IMFEDK 2014  2014 

Characterization and Modeling of Resistive-Transition Phenomena and Electronic Structure of Sputter-Deposition SiO2 Films

R. Yamaguchi, S. Sato, Y. Omura, K. Nakamura

Tech. Dig., WOLTE-11  2014 

Gate-on-Germanium Source (GoGeS)縦型トンネルFETの解析モデルの検討

大村泰久, 佐藤伸吾, Abhijit Mallik

電子情報通信学会 信学技報  2014 

Spectroscopic Electrical Characterization of Post-Resistive-Transition SiO2 Films

R. Yamaguchi, S. Sato, Y. Omura, K. Nakamura

Tech. Dig., IEEE IMFEDK 2014  2014 

非対称ダブル·ゲート横型トンネルFETの解析モデル

呂鴻飛, 佐藤伸吾, 大村泰久, Abhijit Mallik

電子情報通信学会、信学技報  2014 

スパッタ堆積によるSiO2膜の抵抗遷移の特徴に関する考察

山口凜太郎, 佐藤伸吾, 大村泰久, 中村和広

第61回応用物理学会春季学術講演会  2014 

スパッタ堆積によるSiO2膜の抵抗遷移に関する考察-遷移臨界条件-

山口凜太郎, 金剛弘卓, 呂鴻飛, 佐藤伸吾, 大村泰久, 中村和広

第61回応用物理学会春季学術講演会  2014 

Newly developed Test-Element-Group for detecting soft failures of the low-resistance-element using doublly nesting array

S. Sato, H. Shinkawata, A. Tsuda, T. Yoshizawa, T. Ohno

Proceedings of the 2013 IEEE International Conference on Microelectronic Test Structures  2013 

Double-gate Lateral Tunnel FETのデバイスモデル

OMURA,Yasuhisa, SATO,Daiki, SATO,Shingo, Abhijit Mallik

電子情報通信学会 信学技報  2013 

Low-Temperature Behavior Simulations of Phonon-Limited Electron Mobility for Sub-10-nm-Thick SOI MOSFET and GOI MOSFET with (111) or (001) Surface Channel,

T. Yamamura, S. Sato, Y. Omura

Proc. The 8th Int. Workshop on Low Temperature Electronics (WOLTE) (Ilmenau, June, 2008)  2008 

Behavior of Low-Temperature Phonon-Limited Electron Mobility of Double-Gate Field-Effect Transistor with (111) Si Surface Channel,

T. Yamamura, S. Sato, Y. Omura

Ext. Abstr. Int. Conf. Solid State Devices and Mat. (Tsukuba, Sep. 2007)  2007 

Important Aspects of Phonon-Limited Electron Mobility of Double-Gate Field-Effect Transistor or Fin FET with a (111) Si Surface Channel

T. Yamamura, S. Sato, Y. Omura

2007 Int. Meet. Future Electron Devices, Kansai (IMFEDK) (Osaka, 2007)  2007 

Low-Temperature Behavior Simulations of Phonon-Limited Electron Mobility for Sub-10-nm-Thick SOI MOSFET with (111) or (001) Si Surface Channel

T. Yamamura, S. Sato, Y. Omura

Proc. IEEE 2007 Int. SOI Conf. (Indean Wells, Oct., 2007)  2007 

Impact of Band Structure on Phonon-Limited Electron Mobility Behavior for Ultra-Thin GOI MOSFET

T. Yamamura, S. Sato, Y. Omura

Abstr. IEEE 2007 Silicon Nanoelectronics WS (Kyoto, June, 2007)  2007 

Empirical Model of Phonon-Limited Electron Mobility for Ultra-Thin Body SOI MOSFET,

T. Yamamura, S. Sato, Y. Omura

Ext. Abstr. Of 2006 Int. Conf. Solid State Devices and Mat. (Yokohama, 2006)  2006 

Impact of the Schottky Contact on Characterization of Ultra-thin SOI Pseudo-MOS Transistors

S. Sato, K. Komiya, N. Bresson, Y. Omura, S. Cristoloveanu

Proc. 12th Int. Symp. Silicon-on-Insulator Technol. and Devices (The Electrochem. Soc., Canada, Quebec, 2005)  2005 

Detailed Investigation of Geomentrical Factor for Pseudo-MOS Transistor Technique

Proc. 2004 IEEE Int. SOI Conf. (Charsten, USA, Oct. 2004)  2004 

Impact of high-k plug on self-heating effects of SOI MOSFET’s

K. Komiya, T. Kawamoto, S. Sato, Y. Omura

Proc. the 4th Int. Symp. On Advanced Science and Technology of Silicon Materials (Kona, Hawaii, 2004) K-1  2004 

Impact of the Schottky contacts on characterization of Ultra-Thin SOI Pseudo-MOS transistors

S. Sato, K. Komiya, N. Bresson, Y. Omura, S. Cristoloveanu

Proc. the 4th Int. Symp. On Advanced Science and Technology of Silicon Materials (Kona, Hawaii, 2004) K-6,  2004 

Quantum-Mechanical Enhancement of Short-Channel Effects in Ultra-Thin SOI MOSFETs

H. Konishi, S. Sato, K. Komiya, Y. Omura

Ext. Abstr., IEEE 2004 Int. Meeting for Future Electron Dvices, Kansai (IMFEDK, Kyoto, July, 2004)  2004 

Influence of Electrode Materials and their Deposition Method on Switching Characteristics of ReRAM Devices

S.Watanabe, S. Kawata, T. Taniyama, P. Wiśniewski, Y. Omura, S. Sato

2023.11 

The spds*p*+Δ tight binding model for 3C-SiC

S. Kanai, T. Nishikawa, S. Sato

2023.11 

Detailed analysis of electrical components on a layered wafer with an ac pseudo-MOS method,

Y. Yuan, S. Sato

2023.5 

The impact of Carrier Lifetime on the Electrical Characteristics of Z2-FET

S. Kim, S. Sato

2022.11 

Detailed analysis of electrical components on SOI wafer with an ac pseudo-MOS method,

Y. Yuan, S. Sato

2022.11 

The influence of the process parameters on the quality of SiO2 film for the swithing operation of ReRAM devices

T. Taniyama, S. Sato

2022.11 

Modeling the propagation of ac signal on the channel of the pseudo-MOS method

SATO,Shingo

2021.9