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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：SPIE  

This paper demonstrates the impacts of light and ambient gas on the resistance of sputter-deposited non-doped ZnO films. Although the authors have already demonstrated the impact of light from various LEDs with a different wavelength on the resistance of such films, key results were not shown in detail. In this paper, the influence of ambient gas on the resistance and the influence of temperature on resistance are demonstrated in detail, and feasible physics drawn from analysis results are discussed. Physical images of the phenomena are proposed. It is also comprehensively revealed that the film surface condition significantly contributes to the transport characteristics of the film
this is supported by the impact of ambient gas in the dark on the current decay process in the film.

DOI： 10.1117/12.2550791

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Praise Worthy Prize  

The purpose of this paper is to analyze the reason why the gate-to-drain capacitance (Miller capacitance) of a tunnel FET (TFET) is very large, and to reveal key aspects of the capacitance components of TFET. A numerical device simulator is used to compare lateral and vertical TFET performance. It is demonstrated that the Miller capacitance of the devices, particularly the lateral TFET, can be drastically reduced without degrading the drivability, by using gate-to-drain off-set. It is also demonstrated that while vertical TFETs are promising for decreasing the switching delay, they suffer the fatal demerit of poor drivability when scaled. In addition, this paper tackles the numerical modelling of TFET capacitance components in order to appropriately estimate switching delay time of the devices
no reliable model has been proposed for TFETs to date. It is shown that the capacitance model leads to better estimates of switching delay times of TFETs than the conventional estimation method.

DOI： 10.15866/irea.v7i3.17027

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

This paper discusses aspects of gate-To-drain capacitance (Miller capacitance) of lateral tunnel FETs (LTFETs). It is considered how to reduce the mirror capacitance of LTFET.

DOI： 10.1109/IMFEDK.2018.8581961

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Language：English   Publisher：Institute of Physics  

In this study, the important roles of chemical stoichiometry and hot electrons in realizing the stable bipolar resistive transition of sputter-deposited silicon oxide films were demonstrated. It was also clearly demonstrated that the injection of “hot” electrons from the silicon substrate induces stable resistive transitions for a low concentration of suboxide and metallic Si atoms, and that the injection of “cold” electrons from the silicon substrate does not induce stable resistive transitions in spite of the inclusion of metallic Si atoms in the oxide films. However, it was shown that the specific metal top electrode that does not react with oxygen ions is useful as the electron injector and temporal oxygen-ion pocket for the stable resistive transition of sputter-deposited silicon oxide films.

DOI： 10.7567/JJAP.56.041301

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Electrochemical Society Inc.  

Influence of native oxide growth on the top and/or the back surface(s) of the pseudo-MOS structure on impedance is analyzed. This impedance analysis reveals a definite reduction in resistance is achieved with the removal the surface native oxide by HF cleaning. The resistance increased with the time spent after HF treatment. These suggest the native oxide will induce erroneous estimations of surface carrier density when attempting to use the pseudo-MOS structure to extract the universal effective mobility.

DOI： 10.1149/07711.1887ecst

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper proposes a detailed equivalent circuit of the pseudo-MOS capacitor structure and subjects it to impedance spectroscopy. We find, using Cole-Cole plots, that three resistance components, which correspond to interface traps, contact resistance, and bulk traps created near the contact, are observed in measurements of a silicon-on-insulator wafer. The simulation results gained from the detailed equivalent circuit proposed here well match the measurement results over the wide frequency range examined.

DOI： 10.1109/JEDS.2016.2557343

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes a possible threshold voltage definition of lateral tunnel FETs. The method well estimates the threshold condition with high universality given practical bias conditions and device parameters. Device simulations demonstrate that the threshold condition has been physically elucidated.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper uses Cole-Cole plots to analyze the capacitance component of the pseudo-MOSFET as a function of frequency. Measurements of silicon-on-insulator wafers identify three capacitance components. Simulations using an equivalent circuit model of the pseudo MOSFET successfully match the measurement results over a wide range of frequency and can explain the probe-number dependence of impedance characteristic qualitatively.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IOP PUBLISHING LTD  

We use the semi-microscopic theory to elucidate the effective diffusion coefficient of carriers in one-dimensional Si wire devices. In the theoretical model, it is assumed that the primary spectrum of the diffusion process of majority and minority carriers rules the diffusion process; a statistical assessment of the diffusion coefficient is performed using quantum-mechanical analysis. Here the model assumes that the thermalization of carrier transport is ruled by the specific characteristic length. The theory reveals that the diffusion coefficient drastically decreases as the wire width enters the sub-10-nm range. Although it is suggested that the behavior of the diffusion coefficient of such Si wires is related to phonon scattering events in narrow wires, it is not so clear whether it is the dominant mechanism ruling the diffusion coefficient of Si wires. A quantitative prediction of carrier mobility in Si wires is also made on the basis of Einstein's relation, and the model's validity is examined. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.054001

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Electrochemical Society Inc.  

This paper presents a compact model of the Nano-Wire Tunnel Field-Effect Transistor (NW-TFET). We analyze the validity of the previous-reported tunnel probability and our model using an analytical potential model with a depletion approximation. We clarify the difference between the models by using the ratio of channel length to natural length to characterize the NW-TFET. By considering the offset of the gate voltage, the tunnel probability of our model can reproduce the numerically derived one for any channel length near the ON-state. Finally, we present a compact model of the drain current.

DOI： 10.1149/06605.0171ecst

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes the possible physics-based model for the conductive filament (CF) at the low-resistance state (LRS) of thin SiO2 films that were formed by sputtering technique. The closed and analytical current models proposed here are examined by experimental results.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A circuit architecture and measurement technique are proposed to reduce the leakage current that passes through peripheral circuits when examining arrays of resistive elements. We reveal, with the aid of circuit simulations, that high resolution measurements of resistive elements can be realized with the stacked column-selection array and the addition of a leakage-control terminal.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Electrochemical Society Inc.  

This paper proposes an analytical model for the asymmetric double gate (ADG) TFET. The two-dimensional Poisson equation is solved based on a depletion approximation. The two-dimensional potential function is given by appropriate boundary conditions. Internal electric field is calculated from the potential model and the tunnel current is numerically calculated using Kane's tunnel current generation model. We use a commercial TCAD simulator to examine the analytical model.

DOI： 10.1149/06605.0193ecst

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper presents a 2-D potential model for the asymmetric double-gate tunnel FET (ADG-TFET) that well considers the source-channel junction depletion region. The model derives a closed and analytical form derived from the 2D Poisson equation by using the conformal mapping technique. Potential function and electric field function are given by appropriate boundary conditions. We use a commercial TCAD simulator to verify the model.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

An addressable test structure array for detecting soft failures in interconnect vias was developed. Resistive elements exhibiting abnormally high resistance are detected, while suppressing the measurement time, using a doubly nesting array structure. Applying this technique to the development of a 40-nm CMOS technology, a soft failure with about ten times larger than normal via resistance could be efficiently detected and located.

DOI： 10.1109/TSM.2014.2310239

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper demonstrates the electronic structures of SiO2 films in low-resistance state and high-resistance state. The electronic structure is also characterized spectroscopically by means of the current fluctuation.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper considers aspects of low-frequency noise in the inversion-channel SOI nMOSFET and the buried-channel SOI pMOSFET. Analyses suggest that the inversion channel is strongly influenced by interface traps, which also weakly influence the buried-channel. It is demonstrated that such aspects are significant in the subthreshold bias range.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper uses the semi-microscopic theory to elucidate the effective diffusion coefficient of carriers in one-dimensional Si wire devices. The theoretical model assumes that the primary spectrum of the diffusion process of majority and minority carriers rules the diffusion process; a statistical assessment of the diffusion coefficient is performed based on quantum-mechanical analysis. The theory reveals that the diffusion coefficient drastically decreases as the cross-sectional area falls under the sub-10-nm range.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper investigates the electronic structures of sputter-deposition SiO2 films in low-resistance state and high-resistance state at room temperature and low temperature. The electronic structure of post-resistive transition is also characterized spectroscopically by means of the current fluctuation.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：JAPAN SOCIETY APPLIED PHYSICS  

In this study we simulate the impact of silicon layer thickness and temperature on the phonon-limited electron mobility of the inversion layer for ultrathin-body (111) and (001) surface silicon-on-insulator (SOI) layers in single-gate (SG) and double-gate (DG) SOI metal-oxide-semiconductor field-effect transistors (MOSFETs); one-dimensional self-consistent calculations and relaxation time approximations are performed. For a sub-10-nm-thick SOI layer, it is demonstrated that intra-subband phonon scattering at the lowest subband in the inversion layer on the (111) Si surface of the DG SOI MOSFET is strongly suppressed in a medium-to-high effective field (E(eff)) at a low temperature. On the other hand, it is revealed that the contribution of inter-subband phonon scattering in the inversion layer on the (001) Si surface of the DG SOI MOSFET is very large in a medium-to-high E(eff) regardless of temperature. Simulation results suggest that the phonon-limited electron mobility on the (111) Si surface of the DG MOSFET will be highly advantageous for future high-performance low-temperature device applications including space applications. (C) 2009 The Japan Society of Applied Physics DOI: 10.1143/JJAP.48.071204

DOI： 10.1143/JJAP.48.071204

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：JAPAN SOC APPLIED PHYSICS  

In this paper, we apply a finite-difference-method-based mathematical scheme to simulate one-dimensional electron transport, where the parabolic band is assumed to be in the reciprocal lattice space, with arbitrary band orientation. In order to examine the validity of the theoretical scheme, we calculate wave functions of the one-dimensional electron system on a specific semiconductor surface, which has the nondiagonal component of the effective mass tensor in Schrodinger's equation. It is demonstrated that the anisotropic nature of the electron wave function is successfully reproduced with a negligibly small error in comparison with the exact analytical solutions. We characterize the surface orientation dependence of the line electron density and channel capacitance for various rectangular gate-all-around field-effect transistors (FETs). We also address the impact of the specific surface orientation of a semiconductor device on device performance.

DOI： 10.1143/JJAP.47.1706

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：JAPAN SOCIETY APPLIED PHYSICS  

One-dimensional self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility behavior of the inversion layer at room temperature for ultrathin body Si(111) and Ge(001) layers in single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) and germanium-on-insulator (GOI) metal-oxide-semiconductor (MOS) field-effect transistors (FETs). Assuming a 5-nm-thick SOI layer, it is shown that intravalley phonon scattering (acoustic-phonon scattering) in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium and high effective field (E(eff)) values; DG SOI MOSFETs have higher phonon-limited electron mobility than SG SOI MOSFETs. Many simulations strongly indicate that, for medium E(eff) values, the suppression of acoustic-phonon scattering in a 5-nm-thick DG SOI MOSFET primarily stems from the reduction of the form factor (F(00)) value. Although similar phenomena are observed in approximately 7-nm-thick GOI layers with a Ge(001) surface, it is shown that there is little merit in using the Ge(001) surface for DG GOI MOSFETs.

DOI： 10.1143/JJAP.46.7654

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：INST PURE APPLIED PHYSICS  

We propose empirical models of the phonon-limited electron mobility of single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) with (001) or (111) Si surface channels. Electron mobility models are functions of the SOI layer thickness and the effective electric field. The proposed phonon-limited electron mobility models accurately reproduce self-consistent simulation results. The purpose of the study is to produce reliable mobility models that can be applied to commercial device simulators. Using the electron density derived from quantum simulations and the proposed empirical electron mobility models, drain current vs gate voltage (I-d-V-g) and transconductance vs gate voltage (g(m)-V-g) characteristics of SG and DG SOI MOSFETs with 10- and 3-nm-thick SOI layers, (001) or (111) surfaces, are calculated to examine the potential of the proposed mobility models. The results are compared with commercial two-dimensional (2-D) device simulation results (DEESIS simulator). It has been shown that the DESSIS results are not reliable when the device has a sub-10-nm-thick SOI layer. The proposed model, on the other hand, clearly reproduces the effects of Si surface orientation and device structure. The proposed models are useful for a simple estimation of the drive current of various SOI MOSFETs and for reducing the computation time in device simulations and circuit simulations.

DOI： 10.1143/JJAP.46.3463

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：AMER INST PHYSICS  

One-dimensional self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility of the inversion layer at room temperature for ultrathin body Si (111) layers in single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFET's). Assuming a 5-nm-thick SOI layer, it is shown that intravalley phonon scattering (acoustic-phonon scattering) in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium effective field (E-eff) values; DG SOI MOSFETs have higher phonon-limited electron mobility than SG SOI MOSFET's. Many simulations strongly suggest that the suppression of acoustic-phonon scattering in a 5 nm T-SOI DG SOI MOSFET primarily stems from the reduction of the form factor (F-00) value within medium E-eff values. (c) 2007 American Institute of Physics.

DOI： 10.1063/1.271775

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

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Language：English   Publishing type：Research paper (international conference proceedings)  

ID self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility of the inversion layer at room temperature for ultra-thin Si (111), Ge (001) and Ge (111) layers in single-gate (SG) and double-gate (DG) MOSFET's. Assuming a 5-nm-thick SOI layer, it is shown that intra-valley phonon scattering in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium Eeff value
DG devices have higher phonon-limited electron mobility than SG devices. The suppression of intra-valley phonon scattering in a 5-nm TSOI DG device primarily stems from the reduction of the form factor [F00) value within medium Eeff values. Similar aspects of electron mobility expected for SG and DG GOI MOSFET's are also discussed. © The Electrochemical Society.

DOI： 10.1149/1.2728884

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Language：English   Publishing type：Research paper (international conference proceedings)  

We discuss the origins of the transient gate current observed in the pseudo-MOS transistor in order to extract optional semiconductor parameters and its physical mechanisms. We analyze the time evolution of the gate current
its delay time is long even in quasi-static measurements at low gate voltages. Experiments show that the transient gate current characteristics are ruled by the generation-recombination process in the SOI layer and thermionic emission currents through the source and drain contacts. We address how to evaluate the generation-recombination lifetime in the SOI layer from the transient gate current behavior. © The Electrochemical Society.

DOI： 10.1149/1.2728846

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper simulates the transport characteristics of ultrathin silicon-on-insulator MOSFETs, and evaluates the influence of the quantum-mechanical mechanism on the short-channel effects on the basis of the density-gradient model. It is clearly shown that the quantum-mechanical mechanism suppresses the buried-insulator-induced barrier lowering with regard to the subthreshold swing because the surface dark space yields a high-field region in the source region adjacent to the channel. It is also suggested that the quantum-mechanical mechanism enhances the impact of the apparent charge-sharing effect on the threshold voltage because the surface dark space effectively increases the thickness of the gate-oxide layer and buried-oxide layer.

DOI： 10.1109/TED.2006.870274

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：INST PURE APPLIED PHYSICS  

In this paper, we describe the physics-based determination of the carrier effective mass assumed in a density gradient model (DGM). We show that the effective mass assumed in a conventional DGM corresponds to that along the quantization direction assumed in the Schrodinger-Poisson (SP) solver, and that the DGM produces a good quantum correction for a system with a smooth conduction band bottom profile. Assuming an abrupt jump in the conduction band bottom profile of a heterostructure system, the physics-based determination of parameters is required to obtain agreement with the SP solver result. Whether the physical meaning of the effective mass holds is examined for the two-fluid description of the DGM.

DOI： 10.1143/JJAP.45.689

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

The paper describes the impact of pseudo-MOS technique on threshold and fiatband voltages, and why the threshold and flatband voltages depend on silicon-on-insulator (SOI) layer thickness. Our measurements and simulations suggest that the band-offset-induced depletion beneath the source contact obstructs the local formation of the inversion layer at the SOI/buried oxide interface; this effect becomes significant when the SOI layer thickness is reduced. The SOI layer thickness dependence of flatband voltage is analyzed in a similar manner. The temperature dependence of threshold and fiatband voltages is also addressed.

DOI： 10.1109/TED.2005.852173

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. The sample size and probe-pressure effects on the drain current are revisited. It is demonstrated that the geometrical factor is significantly affected by the probe-to-edge distance and probe pressure. The correct geometrical factor, reflecting silicon island size, and probe pressure effects, is extracted from systematic experimental results and used to determine the actual carrier mobility.

DOI： 10.1109/TED.2005.843970

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Language：English   Publishing type：Research paper (international conference proceedings)  

We describe a physical mechanism to better understand the threshold voltage and flat-band voltage of the pseudo-MOS, and show why the threshold and flat-band voltages depend on SOI layer thickness. Our measurements and simulations suggest that the band-offset-induced depletion layer beneath the source contact obstructs the local formation of the inversion layer at the SOI/buried oxide interface
this effect becomes significant when the SOI layer thickness is reduced. The SOI layer thickness dependence of flat-band voltage is analyzed in a similar manner. The temperature dependence of threshold and flat-band voltages is also addressed.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

A novel SOI device structure that suppresses self-heating effects is proposed. Since it provides effective thermal paths from source to substrate and from drain to substrate, it successfully suppresses the lattice temperature rise throughout the whole device. Since the buried insulator is SiO2, it is almost free from the fabrication issues and performance issues in use of high-k material such as high internal charge density, high interface trap density, and drain-induced barrier lowering; the proposed device structure will be easy to fabricate using current trench isolation techniques.

DOI： 10.1109/TED.2004.839874

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper discusses the importance of controlling the lateral diffusion of impurities around the source and drain (S/D) junctions in sub-100-nm channel single-gate silicon-on-insulator (SOI) MOSFETs. Since any reduction in lateral diffusion length must consider the tradeoff between drivability and short-channel effect with regard to the threshold voltage, optimization of lateral diffusion length is essential in the device design stage. We note that the net performance improvement offered by device-scaling is quite limited, even if lateral diffusion length is optimized in some way. It seems obvious that high-kappa materials are needed in order to improve net device performance in the sub-100-nm technology regime. In addition, with regard to the impact of the thermal budget on lateral diffusion control, new doping materials such as Sb and In, will be required in the near future. In the case of nMOSFET, however, advanced structures, such as an elevated layer, and advanced annealing process are needed to provide enhanced control of S/D diffusion regions.

DOI： 10.1109/TED.2004.827360

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

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Venue：Online & Avanti Kyoto Hall, Kyoto,Japan  

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