Japan Society for the Promotion of Science

2004.4 - 2005.11

電子情報通信学会   英文誌特集号 (2025VL) 編集幹事  

2025.1 - 2026.3   

International Conference on Solid State Devices and Materials   Area Vice-Chair  

2024.11 - Present   

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)   2023.12

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

2023 20th International SoC Design Conference (ISOCC)   2023.10

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

2023 IEEE 15th International Conference on ASIC (ASICON)   2023.10

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

IEICE Electronics Express   20 ( 14 )   20230238 - 20230238   2023.7

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS.

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

ASICON   1 - 2   2023

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS.

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

ISOCC   13 - 14   2023

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

ICECS   1 - 4   2023

Low-power and Small-area 4-ch 25-Gb/s Transimpedance Amplifiers in 65-nm CMOS Process

Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

IEICE Electronics Express   2023

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)   2022.10

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura

2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)   2022.8

Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit Reviewed

Yasuhiro Takahashi, Daisuke Ito, Makoto Namamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

Electronics (Switzerland)   11 ( 6 )   2022.3

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

29th IEEE International Conference on Electronics, Circuits and Systems   1 - 4   2022

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier.

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura

International Conference on Electronics, Information, and Communication(ICEIC)   1 - 4   2022

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura

2022 International Conference on Electronics, Information, and Communication, ICEIC 2022   2022

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad.

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura

65th IEEE International Midwest Symposium on Circuits and Systems(MWSCAS)   1 - 4   2022

Dynamic Memory Access Control for Accelerating FPGA-based Image Processing

Nishiguchi, K., Inoue, T., Yamazaki, R., Ogohara, K., Tsuchiya, A., Kishine, K.

Journal of Semiconductor Technology and Science   21 ( 1 )   2021

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks.

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

28th IEEE International Conference on Electronics, Circuits, and Systems(ICECS)   1 - 6   2021

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

2021 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021 - Proceedings   2021

Design method for active-shunt-feedback type inductorless low-noise amplifiers in 65-nm CMOS

Inoue, T., Tsuchiya, A., Kishine, K.

Journal of Semiconductor Technology and Science   20 ( 2 )   2020

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS Reviewed

Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

2019 32nd IEEE International System-on-Chip Conference (SOCC)   2019.9

Impact of on-chip inductor and power-delivery-network stacking on signal and power integrity Reviewed

Tsuchiya, A., Hiratsuka, A., Inoue, T., Kishine, K., Onodera, H.

IEICE Transactions on Electronics   E102C ( 7 )   573 - 579   2019.7

FPGA-based binary labeling signal transmission system

Inoue, T., Nomura, K., Noguchi, R., Koda, N., Tsuchiya, A., Kishine, K.

Journal of Semiconductor Technology and Science   19 ( 3 )   2019

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation Reviewed

Akitaka Hiratsuka, Akira Tsuchiya, Kcnji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)   69 - 72   2018.11

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology Reviewed

Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)   751 - 954   2018.8

Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net Reviewed

A. Tsuchiya, A. Hiratsuka, T. Inoue, K. Kishine, H. Onodera

22nd IEEE Workshop on Signal and Power Integrity   1 - 4   2018.5

A 25-Gb/s 13 mW Clock and Data Recovery Using C2MOS D-Flip-Flop in 65-nm CMOS Reviewed

R. Noguchi, K. Furuichi, H. Uemura, T. Inoue, A. Tsuchiya, K Kishine, H. Katsurai, S. Nakamoto, M. Nakamura

The 2018 International Symposium on VLSI Design, Automation and Test (2018 VLSI-DAT)   2018.4

Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS Reviewed

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura

International SoC Design Conference (ISOCC2017)   2017.11

Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication Reviewed

Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)   795 - 798   2017.8

高密度・高速光インターコネクトに向けたCMOS光受信回路の開発

土谷亮, 中尾拓也, 中野慎介, 野河正史, 野坂秀之, 小野寺秀俊

信学技報   116 ( 467 )   CAS2016-124   2017.2

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS Reviewed

T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto

IEIE Transactions on Smart Signal and Computing   5 ( 3 )   207 - 214   2016.6

A 32-Gb/s output buffer circuit with doubled pre-emphasis in 65-nm CMOS Reviewed

T. Tanaka, K. Kishine, D. Omoto, A. Tsuchiya, H. Inaba

International Conference on Electronics, Information, and Communication   2016.1

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector Reviewed

Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya

2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)   61 - 62   2016

Impact of anomalous skin effect on metal wire for terahertz integrated circuit Reviewed

Akira Tsuchiya, Hidetoshi Onodera

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)   217 - 219   2015.8

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage Reviewed

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS   E98C ( 6 )   504 - 511   2015.6

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS Reviewed

Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS   62 ( 5 )   1288 - 1295   2015.5

A wireless neural recording system with a precision motorized microdrive for freely behaving animals Reviewed

Taku Hasegawa, Hisataka Fujimoto, Koichiro Tashiro, Mayu Nonomura, Akira Tsuchiya, Dai Watanabe

SCIENTIFIC REPORTS   5   7853   2015.1

Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation Reviewed

Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015)   181 - 185   2015

A 25-Gb/s 480-mW CMOS Modulator Driver using Area-Efficient 3D Inductor Peaking Reviewed

Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura

2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   253 - 256   2015

On-Chip Coupled Inductor for Area-Efficient Inductive Peaking Reviewed

Akira Tsuchiya, Taro Amagai, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera

Thailand-Japan Microwave   2014.11

PLL の物理レイアウト自動生成を目指した設計手法 Reviewed

釡江典裕, 土谷亮, 石原亨, 小野寺秀俊

情 報処理学会DA シンポジウム   2014.8

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops

Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai

Proceedings - IEEE International Symposium on Circuits and Systems   2704 - 2707   2014.6

Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure Reviewed

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS   E97C ( 4 )   325 - 331   2014.4

Cell-based Physical Design Automation for Analog and Mixed Signal Application Reviewed

Norihiro Kamae, Islam A.K.M Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera

International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)   13   2014.3

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation Reviewed

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E97A ( 3 )   734 - 740   2014.3

Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop Reviewed

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E97A ( 3 )   768 - 776   2014.3

A Body Bias Generator with Wide Supply-Range down to Threshold Voltage for Within-Die Variability Compensation Reviewed

Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Hidetoshi Onodera

2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   53 - 56   2014

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops Reviewed

Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   2704 - 2707   2014

25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS Reviewed

Tomoki Tanaka, Keiji Kishine, Hiromi Inaba, Akira Tsuchiya

2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)   94 - 95   2014

\Analysis of Radiation-Induced Timing Vulnerability on Phase- locked Loops Reviewed

S.N. Kim, A. Tsuchiya, H. Onodera

情報処理学会DA シンポジウム   2013.8

Impact of skin effect on loss modeling of on-chip transmission-line for terahertz integrated circuits Reviewed

Akira Tsuchiya, Hidetoshi Onodera

IMFEDK 2013 - 2013 International Meeting for Future of Electron Devices, Kansai   106 - 107   2013

A slow-wave transmission line with thin pillars for millimeter-wave CMOS Reviewed

Taro Amagai, Akira Tsuchiya, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera

2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013   2013

Perturbation-immune radiation-hardened PLL with a switchable DMR structure Reviewed

Sin Nyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013   128 - 132   2013

A 25-Gb/s LD Driver with Area-Effective Inductor in a 0.18-mu m CMOS Reviewed

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)   105 - 106   2013

Advanced RF and analog integrated circuits for fourth generation wireless communications and beyond Reviewed

Ramesh Pokharel, Leonid Belostotski, Akira Tsuchiya, Ahmed Allam, Mohammad S. Hashmi

International Journal of Microwave Science and Technology   2013

Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation Reviewed

Islam A. K. M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING   25 ( 4 )   571 - 580   2012.11

Dual-PLL based on Temporal Redundancy for Radiation-Hardening Reviewed

SinNyoung KIM, Akira TSUCHIYA, Hidetoshi ONODERA

Proceedings of 10th International Workshop on Radiation Effects on Semiconductor Devices for Space Applications   2012.10

Modeling of Single-Event Failures in Dividerand PFD of PLLs based on Jitter Analysis Reviewed

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

13th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep 2012.   2012.9

Evaluation of Single-Event Vulnerability in Analog and Digital Signals of PLL based on Error-Categorization

KIM SinNyoung, TSUCHIYA Akira, ONODERA Hidetoshi, ONODERA Hidetoshi

DA Symposium   2012 ( 5 )   151 - 156   2012.8

チップ内基板バイアス生成回路のモジュール化設計 Reviewed

釡江典裕, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム2012論文集, pp. 55-60, Aug 2012.   2012.8

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System Reviewed

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E95A ( 2 )   479 - 486   2012.2

Impact of radiation loss in on-chip transmission-line for terahertz applications Reviewed

Akira Tsuchiya, Hidetoshi Onodera

2012 IEEE 16th Workshop on Signal and Power Integrity, SPI 2012 - Proceedings   125 - 128   2012

A 16Gb/s Area-Efficient LD Driver with Interwoven Inductor in a 0.18 mu m CMOS Reviewed

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)   561 - +   2012

A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation Reviewed

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

2012 IEEE ASIAN SOLID STATE CIRCUITS CONFERENCE (A-SSCC)   389 - 392   2012

Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors Reviewed

A. Tsuchiya, T. Kuboki, Y. Ohtomo, K. Kishine, S. Miyawaki, M. Nakamura, H. Onodera

2011 International SoC Design Conference, ISOCC 2011   36 - 39   2011.11

Evaluation of future PLL performance by predictive model card reflecting ITRS technology scaling

金 信寧, 土谷 亮, 小野寺 秀俊

DAシンポジウム2011年論文集, pp.105-110   105 - 110   2011.8

Gradient Resistivity Method for Numerical Evaluation of Anomalous Skin Effect Reviewed

Akira Tsuchiya, Hidetoshi Onodera

2011 15TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS (SPI)   139 - 142   2011

A 10.3Gbps transimpedance amplifier with mutually coupled inductors in 0.18-μm CMOS Reviewed

S. Miyawaki, M. Nakamura, A. Tsuchiya, K. Kishine, H. Onodera

2011 International SoC Design Conference, ISOCC 2011   223 - 226   2011

Variation-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variation Reviewed

Islam A. K. M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

2011 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS)   153 - 157   2011

An area effective forward/reverse body bias generator for within-die variability compensation Reviewed

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011   217 - 220   2011

レイアウト制約が性能と製造性に与える影響 Reviewed

北島和彦, 砂川洋輝, 土谷亮, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集   2010 ( 7 )   221 - 226   2010.8

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells

Sunagawa Hiroki, Terada Haruhiko, Tsuchiya Akira, Kobayashi Kazutoshi, Onodera Hidetoshi

Information and Media Technologies   5 ( 2 )   424 - 433   2010

Measurement of on-chip transmission-line with stacked split-ring resonators Reviewed

Akira Tsuchiya, Hidetoshi Onodera

2010 IEEE 14th Workshop on Signal Propagation on Interconnects, SPI 2010 - Proceedings   137 - 140   2010

A 16Gbps Laser-Diode Driver with Interwoven Peaking Inductors in 0.18-mu m CMOS Reviewed

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010   2010

A 16Gbps Laser-Diode Driver with Interwoven Peaking Inductors in 0.18-mu m CMOS Reviewed

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010   2010

A design procedure of predictive RF MOSFET model for compatibility with ITRS Reviewed

Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

Proceedings - IEEE International SOC Conference, SOCC 2010   396 - 399   2010

Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability Reviewed

A.K.M Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

Tau Workshop 2010, Mar 2010.   2010

Effect of regularity-enhanced layout on variability and circuit performance of standard cells Reviewed

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IPSJ Transactions on System LSI Design Methodology   3   130 - 139   2010

Statistical Gate Delay Model for Multiple Input Switching Reviewed

Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 12 )   3070 - 3078   2009.12

Effect of dummy fills on characteristics of passive devices in CMOS millimeter-wave circuits Invited Reviewed

A. Tsuchiya, H. Onodera

ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC   296 - 299   2009.10

遅延モニタ回路によるプロセス変動量の推定

Islam A.K.M. Mahfuzul, 土谷亮, 小林和淑, 小野寺秀俊

DAシンポジウム2009   127 - 132   2009.8

チップ内ばらつきが順序セルの動作特性に与える影響 Reviewed

砂川洋輝, 土谷亮, 小林和淑, 小野寺秀俊

情報処理学会DA シンポジウム   2009.8

Effect of Underlayer Dummy Fills on On-Chip Transmission Line Reviewed

Akira Tsuchiya, Hidetoshi Onodera

2009 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS   126 - 129   2009

Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells Reviewed

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2   195 - 200   2009

On-Chip Metamaterial Transmission-Line Based on Stacked Split-Ring Resonator for Millimeter-Wave LSIs Reviewed

Akira Tsuchiya, Hidetoshi Onodera

APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5   1458 - 1461   2009

High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication Reviewed

Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng

PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009   385 - +   2009

Patterned Floating Dummy Fill for On-Chip Spiral Inductor Considering the Effect of Dummy Fill Reviewed

Akira Tsuchiya, Hidetoshi Onodera

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES   56 ( 12 )   3217 - 3222   2008.12

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration Reviewed

Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 12 )   3474 - 3480   2008.12

リングオシレータアレイによるゲート遅延ばらつきの評価とモデル化 Reviewed

寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集   2008 ( 7 )   199 - 204   2008.8

Accurate estimation of the worst-case delay in statistical static timing analysis Reviewed

Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

IPSJ Transactions on System LSI Design Methodology   1   116 - 125   2008.8

レイアウト規則性が回路性能とばらつきに及ぼす影響の評価 Reviewed

砂川洋輝, 寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集   2008 ( 7 )   67 - 72   2008.8

Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis

Terada Haruhiko, Fukuoka Takayuki, Tsuchiya Akira, Onodera Hidetoshi

Information and Media Technologies   3 ( 4 )   729 - 738   2008

On-chip High Performance Signaling Using Passive Compensation Reviewed

Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng

2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN   182 - +   2008

Dummy Fill Insertion Considering the Effect on High-Frequency Characteristics of Spiral Inductors Reviewed

Akira Tsuchiya, Hidetoshi Onodera

2008 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-4   1049 - 1052   2008

Statistical gate delay model for Multiple Input Switching Reviewed

Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2   205 - 210   2008

同時スイッチングを考慮した統計的遅延解析 Reviewed

福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集   2007 ( 7 )   13 - 18   2007.8

統計的遅延解析における遅延分布間の最大値計算手法 Reviewed

寺田晴彦, 福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集   2007 ( 7 )   7 - 12   2007.8

Optimal termination of on-chip transmission-lines for high-speed signaling Reviewed

Tsuchiya, Akira, Hashimoto, Masanori, Onodera, Hidetoshi

IEICE TRANSACTIONS ON ELECTRONICS   E90C ( 6 )   1267 - 1273   2007.6

Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed

Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS   E90C ( 6 )   1274 - 1281   2007.6

Analytical estimation of interconnect loss due to dummy fills Reviewed

20   19 - 22   2007.4

Effect of Dummy Fills on High frequency characteristics of Spiral Inductor Reviewed

Akira Tsuchiya, Hidetoshi Onodera

14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007), pp.256-260, Oct 2007.   2007

Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed

T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006   227 - 230   2007

Effect of dummy fills on high-frequency characteristics of on-chip interconnects Reviewed

Akira Tsuchiya, Hidetoshi Onodera

Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006   275 - 278   2007

Worst-case Delay Analysis Considering the Variability of Transistors and Interconnects Reviewed

Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

ISPD'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN   35 - 41   2007

Measurement of interconnect loss due to dummy fills Reviewed

Akira Tsuchiya, Hidetoshi Onodera

2007 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS   241 - 244   2007

Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration Reviewed

Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007   869 - 872   2007

A 10Gbps/channel on-chip signaling circuit with an impedance-unmatched CML driver in 90nm CMOS technology Reviewed

Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera

PROCEEDINGS OF THE ASP-DAC 2007   120 - +   2007

Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed

Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 12 )   3560 - 3568   2006.12

Interconnect RL extraction based on transfer characteristics of transmission-line Reviewed

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 12 )   3585 - 3593   2006.12

<大学の研究・動向> 高度情報化社会を支える集積回路

小野寺 秀俊, 小林 和淑, 土谷 亮

Cue : 京都大学電気関係教室技術情報誌   16   8 - 11   2006.10

トランジスタと配線構造のばらつきを考慮した遅延時間のワーストケース解析 Reviewed

福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集   2006 ( 7 )   13 - 18   2006.7

Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed

19   387 - 392   2006.4

Performance prediction of on-chip high-speed signaling Reviewed

19   393 - 398   2006.4

Alternate self-shielding for high-speed and reliable on-chip global interconnect Reviewed

Y Yuyama, A Tsuchiya, K Kobayashi, H Onodera

IEICE TRANSACTIONS ON ELECTRONICS   E89C ( 3 )   327 - 333   2006.3

Analytical estimation of interconnect loss due to dummy fills Reviewed

Akira Tsuchiya, Hidetoshi Onodera

ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING   149 - +   2006

Low-Power Design of CML Drivers for On-Chip Transmission-Lines Reviewed

Akira Tsuchiya, Takeshi Kuboki, Hidetoshi Onodera

SASIMI2006,pp. 177-182   2006

Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Reviewed

T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

International Workshop on Compact Modeling, pp. 51-56, 2006.   2006

Interconnect RL extraction at a single representative frequency Reviewed

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS   2006   515 - 520   2006

CMLを用いたオンチップ長距離高速信号伝送技術の開発

土谷 亮, 新名 亮規, 橋本 昌宜, 小野寺 秀俊

第9回システムLSIワークショップ, pp.275--278, Nov 2005.   2005.11

A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection Reviewed

TSUCHIYA Akira

Kyoto University   2005.11

Performance limitation of on-chip global interconnects for high-speed signaling Reviewed

A. Tsuchiya, M. Hashimoto, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E88A ( 4 )   885 - 891   2005.4

オンチップ高速信号伝送における終端抵抗決定手法 Reviewed

土谷 亮, 橋本 昌宜, 小野寺 秀俊

第18回 回路とシステム軽井沢ワークショップ, pp.425-430, Apr 2005.   2005

Design guideline for resistive termination of on-chip high-speed interconnects Reviewed

A Tsuchiya, M Hashimoto, H Onodera

CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE   2005   613 - 616   2005

Performance prediction of on-chip high-throughput global signaling Reviewed

Masanori Hashimoto, Akira Tsuchiya, Akinori Shinmyo, Hidetoshi Onodera

IEEE Topical Meeting on Electrical Performance of Electronic Packaging   2005   79 - 82   2005

Return path selection for loop RL extraction Reviewed

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2   2   1078 - 1081   2005

Substrate loss of on-chip transmission-lines with power/ground wires in lower layer Reviewed

A Tsuchiya, M Hashimoto, H Onodera

SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS   2005   201 - 202   2005

配線の伝達特性に基づく抽出周波数決定手法 Reviewed

土谷 亮, 橋本 昌宜, 小野寺 秀俊

DAシンポジウム 2005, pp.169-174, Aug 2005.   2005

Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics Reviewed

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005.   2005

配線RL抽出におけるリターンパス選択手法 Reviewed

土谷 亮, 橋本 昌宜, 小野寺 秀俊

DAシンポジウム 2004, pp.175-180, Jul 2004.   2004

Performance prediction of on-chip high-throughput global signaling Reviewed

M Hashimoto, A Tsuchiya, A Shinmyo, H Onodera

ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING   79 - 82   2004

Performance limitation of on-chip global interconnects for high-speed signaling Reviewed

A. Tsuchiya, Y. Gotoh, M. Hashimoto, H. Onodera

Proceedings of the Custom Integrated Circuits Conference   489 - 492   2004

On-chip global signaling by wave pipelining Reviewed

M Hashimoto, A Tsuchiya, H Onodera

ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING   311 - 314   2004

オンチップ伝送線路のリターン電流分布が信号波形に与える影響 — 平衡・不平衡伝送の比較 — Reviewed

土谷 亮, 橋本 昌宜, 小野寺 秀俊

第17回 回路とシステム軽井沢ワークショップ, pp.567-572, Apr 2004.   2004

Representative frequency for interconnect R(f)L(f)C extraction Reviewed

A Tsuchiya, M Hashimoto, H Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E86A ( 12 )   2942 - 2951   2003.12

Representative frequency for interconnect R(f)L(f)C extraction Reviewed

A Tsuchiya, M Hashimoto, H Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E86A ( 12 )   2942 - 2951   2003.12

オンチップ高速信号配線における波形歪みの影響

土谷 亮, 橋本 昌宜, 小野寺 秀俊

2003.9

周辺配線の影響を考慮したオンチップ高速信号伝送用配線構造 Reviewed

土谷 亮

京都大学   2003.2

Representative Frequency for Interconnect R(f)L(f)C Extraction Reviewed

Tsuchiya, A., Hashimoto, M., Onodera, H.

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences   E86-A ( 12 )   691 - 696   2003

配線R(f)L(f)C抽出のための代表周波数決定手法 Reviewed

土谷 亮, 橋本 昌宜, 小野寺 秀俊

第16回 回路とシステム軽井沢ワークショップ, pp.61-66, Apr 2003.   2003

直交配線を持つオンチップ伝送線路の特性評価 Reviewed

土谷 亮, 橋本 昌宜, 小野寺 秀俊

DA シンポジウム 2003, pp.133-138, Jul 2003.   2003

VLSI配線の伝送線路特性を考慮した駆動力決定手法 Reviewed

土谷 亮, 橋本 昌宜, 小野寺 秀俊

情報処理学会論文誌   2002

長距離高速信号伝送を可能にするVLSI配線構造の検討 Reviewed

平松 大輔, 土谷 亮, 橋本 昌宜, 小野寺 秀俊

DA シンポジウム 2002, pp.155-160, Jul 2002.   2002

Interconnect structures for high-speed long-distance signal transmission Reviewed

M Hashimoto, D Hiramatsu, A Tsuchiya, H Onodera

15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS   426 - 430   2002

VLSI配線の伝送線路化を考慮した駆動力決定手法 Reviewed

土谷 亮, 小野寺 秀俊

DA シンポジウム 2001, pp.241-246, Jul 2001.   2001

Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects Reviewed

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

10th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2001), pp.377-381, Oct 2001.   2001

A Design of Multi-stage RGC-TIA Circuit having a Local Feedback

高橋康宏, 伊藤大輔, 中村誠, 土谷亮, 井上敏之, 岸根桂路

電子情報通信学会大会講演論文集(CD-ROM)   2022   2022

CMOS Optical Receiver for High Density and High Speed Optical Interconnection

116 ( 468 )   59 - 62   2017.2

C-12-26 A 25-Gb/s 480-mW 3.3-Vpp CMOS Modulator Driver with a Compact Size

Nakano Shinsuke, Nogawa Masafumi, Tsuchiya Akira, Onodera Hidetoshi, Nosaka Hideyuki

Proceedings of the IEICE General Conference   2016 ( 2 )   99 - 99   2016.3

インバータ増幅段によるレギュレーティッドカスコード型トランスインピーダンスアンプの広帯域化

藤原将倫, 土谷 亮, 中野慎介, 野河正史, 野坂秀之, 小野寺秀俊

電子情報通信学会技術報告書   IEICE-115 ( 477(ICD) )   229 - 233   2016.3

Meta-Surface Structure by Integrated Circuit Technology for Terahertz Wave Generation

TSUCHIYA Akira

IEICE technical report. Microwaves   114 ( 498 )   113 - 116   2015.3

C-12-43 Measurement Results of 25-Gbit/s Output Buffer Circuit with Transmit Pre-emphasis

Tanaka Tomoki, Kishine Keiji, Tsuchiya Akira, Omoto Daichi, Inaba Hiromi

Proceedings of the IEICE General Conference   2015 ( 2 )   104 - 104   2015.2

C-12-39 Low Noise VCO with Inductive Peaking in 65nm-CMOS

Inoue Hiroshi, Kishine Keiji, Tsuchiya Akira, Inaba Hiromi

Proceedings of the IEICE General Conference   2014 ( 2 )   103 - 103   2014.3

Analysis of Radiation-Induced Errors in PLL based on Behavioral Modeling

KIM SinNyoung, FUJITA Tomohiro, TSUCHIYA Akira, ONODERA Hidetoshi

Technical report of IEICE. VLD   113 ( 454 )   131 - 136   2014.3

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation (Special Section on Analog Circuit Techniques and Related Topics)

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   97 ( 3 )   734 - 740   2014.3

Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop (Special Section on Analog Circuit Techniques and Related Topics)

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   97 ( 3 )   768 - 776   2014.3

Invited : Modeling Issues of On-Chip Transmission-Line for Terahertz Integrated Circuits

TSUCHIYA Akira, ONODERA Hidetoshi

IEICE technical report. Microwaves   112 ( 459 )   93 - 96   2013.3

トランジスタサイズに着目した微細CMOS D-FF回路の高速化設計手法

浜田 泰輔, 井上 洋, 岸根 桂路, 土谷 亮, 久保木 猛, 稲葉博美

電子情報通信学会総合大会, C-12-8, Mar 2013.   2013   2013.3

ミリ波帯オンチップ伝送線路における下層シールドの影響

雨貝太郎, 土谷亮, 中野慎介, 野河正史, 小泉弘, 小野寺秀俊

電子情報通信学会総合大会, C-12-19, Mar 2013.   2013.3

インダクティブピーキングを利用したリング型VCOの低ジッタ化に関する研究

井上 洋, 浜田 泰輔, 岸根 桂路, 中野 慎介, 中村 誠, 土谷 亮, 久保木 猛, 稲葉 博美

電子情報通信学会総合大会, C-12-65, Mar 2013.   2013   2013.3

レギュレーティッドカスコードを用いた広帯域フィードバック型トランスインピーダンスアンプ

申 東潤, 土谷 亮, 小野寺秀俊

2012年電子情報通信学会ソサイエティ大会, C-12-3, Sep 2012   2012.9

C-12-51 A DA Converter Circuit for Fine-Grain Body Bias Control

Kamae Norihiro, Tsuchiya Akira, Onodera Hidetoshi

Proceedings of the IEICE General Conference   2012 ( 2 )   123 - 123   2012.3

C-12-61 An Analytical Method of Jitter Prediction for Inductive-peaked Circuits

Enami Tetsuya, Miyawaki Shigekazu, Tsuchiya Akira, Onodera Hidetoshi

Proceedings of the IEICE General Conference   2012 ( 2 )   133 - 133   2012.3

細粒度基板電圧制御に用いるDA変換器

釡江 典裕, 土谷 亮, 小野寺 秀俊

2012年電子情報通信学会総合大会, C-12-51, Mar 2012.   2012.3

完全差動回路構成GVCOの高速化設計

川中 啓敬, 岸根 桂路, 土谷 亮, 小野寺 秀俊

2012年電子情報通信学会総合大会, C-12-46, Mar 2012.   2012.3

Effect of Anomalous Skin Effect on Transmission-Line Loss

TSUCHIYA Akira, ONODERA Hidetoshi

111 ( 351(MW2011 125-141) )   77 - 81   2011.12

Development of Procedure for Modeling MOSFET Compatible with ITRS : Noise and I-V Characteristics Modeling for RF/Analog MOSFET

KIM Sin-Nyoung, TSUCHIYA Akira, ONODERA Hidetoshi

IEICE technical report   110 ( 344 )   119 - 123   2010.12

基板電圧の制御回路とその面積オーバヘッド

釡江典裕, 土谷亮, 小野寺秀俊

2010年電子情報通信学会ソサイエティ大会, C-12-22, Sep 2010.   2010.9

MOSトランジスタの基板抵抗がインダクティブピーキング回路の周波数特性に与える影響

宮脇成和, 土谷亮, 小野寺秀俊

2010年電子情報通信学会ソサイエティ大会, C-12-26, Sep 2010.   2010.9

C-12-27 Development of Design Process for RF MOSFET Model in the Future Technology

KIM SinNyoung, TSUCHIYA Akira, ONODERA Hidetoshi

Proceedings of the Society Conference of IEICE   2010 ( 2 )   88 - 88   2010.8

ランダムばらつきがD-FFのタイミング制約に与える影響

砂川洋輝, 土谷亮, 小野寺秀俊

電子情報通信学会総合大会   C-12-61 - C-12-61   2010.3

Bandwidth Enhancement for TIA with Mutually Coupled Inductors

OKUMURA Yoshihiro, NAKAMURA Makoto, KISHINE Keiji, TSUCHIYA Akira, ONODERA Hidetoshi

IEICE technical report   109 ( 336(ICD2009 76-105) )   157 - 161   2009.12

レイアウト規則性導入によるパターン転写精度の改善効果

砂川 洋輝, 土谷 亮, 小野寺 秀俊

2008年電子情報通信学会ソサイエティ大会   ( C-12-40 )   109 - 109   2008.9

Modeling of On-Chip Transmission-Line for Millimeter Wave CMOS Circuits

土谷 亮, 小野寺 秀俊

2008年電子情報通信学会ソサイエティ大会   ( CK-2-10 )   SS-18 - SS-19   2008.9

オンチップ差動伝送線路の構造と下層配線からのノイズの関係

久保木猛, 土谷亮, 小野寺秀俊

電子情報通信学会大会講演論文集   2008   108   2008.9

Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver

KUBOKI Takeshi, TSUCHIYA Akira, ONODERA Hidetoshi

IEICE Trans. Electron., C   90 ( 6 )   1274 - 1281   2007.6

Effect of Dummy Fill on High-Frequency Characteristics of On-Chip Interconnects

TSUCHIYA Akira, ONODERA Hidetoshi

IEICE technical report   107 ( 32 )   55 - 59   2007.5

A-3-9 Eye-pattern Evaluation of On-chip Interconnects with Intentional Shunt Conductance

Jangsombatsiri Siriporn, Hashimoto Masanori, Tsuchiya Akira, Zhu Haikun, Cheng Chung-Kuan

Proceedings of the IEICE General Conference   2007   99 - 99   2007.3

オンチップ差動伝送線路における下層配線からのノイズの影響

久保木猛, 土谷亮, 小野寺秀俊

電子情報通信学会大会講演論文集   2007   2007

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line

TSUCHIYA Akira, HASHIMOTO Masanori, ONODERA Hidetoshi

IEICE transactions on fundamentals of electronics, communications and computer sciences   89 ( 12 )   3585 - 3593   2006.12

A-3-12 Comparison of DVS and Power Gating in Future Process

SEKI Ryohei, TSUCHIYA Akira, ONODERA Hidetoshi

Proceedings of the Society Conference of IEICE   2006   56 - 56   2006.9

A-3-17 A Predictive Transistor Model Based on ITRS Roadmap

UEMURA Shinichiro, TSUCHIYA Akira, HASHIMOTO Masanori, ONODERA Hidetoshi

Proceedings of the IEICE General Conference   2006   81 - 81   2006.3

A-3-13 Buffer Insertion for Statistical Delay Minimization Considering Interconnect and Transistor Variability

FUKUOKA Takayuki, TSUCHIYA Akira, ONODERA Hidetoshi

Proceedings of the IEICE General Conference   2006   77 - 77   2006.3

Analytical Performance Estimation of On-chip Global Interconnects for High-speed Signaling

TSUCHIYA Akira, HASHIMOTO Masanori, ONODERA Hidetoshi

Technical report of IEICE. VLD   104 ( 709 )   49 - 54   2005.3

A-3-12 Substrate Loss of On-chip Transmission-lines with P/G Grid in Lower Layer

TSUCHIYA Akira, HASHIMOTO Masanori, ONODERA Hidetoshi

Proceedings of the IEICE General Conference   2005   77 - 77   2005.3

オンチップ高速信号伝送用線路の解析的性能評価

土谷 亮, 橋本 昌宜, 小野寺 秀俊

信学技報, vol. 104, No. 709, pp. 49-54, Mar 2005.   2005.3

Effects of orthogonal layer interconnects on coupling with interconnects in a lower layer

A. Tsuchiya, M. Hashimoto, H. Onodera

Proc. IEICE General Conference   ( A-3-14 )   81   2003.3

Effects of orthogonal layer interconnects on LSI interconnect inductance

A. Tsuchiya, M. Hashimoto, H. Onodera

Proc. IEICE General Conference   ( A-3-23 )   102   2002.3

Deterioration of Circuit Design for High-Performance Long Interconnects Based on RC Model

A. Tsuchiya, M. Hashimoto, H. Onodera

Proceedings of the 2001 Engineering Sciences Society Conference of IEICE   ( A-3-6 )   60 - 60   2001.9

SKILL言語による光通信用高速アンプのレイアウト自動生成に関する検討

土谷 亮, 盛 健次, 小野寺 秀俊

第37回アナログRF研究会  2014.12 

On-Chip Coupled Inductor for Area-Efficient Inductive Peaking Invited International conference

Akira Tsuchiya, Taro Amagai, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera

Thailand-Japan Microwave  2014.11 

電磁界解析における異常表皮効果の扱いに関する考察

土谷 亮, 小野寺 秀俊

第35回アナログRF研究会  2014.3 

Modeling Issues of On-Chip Transmission-Line for Terahertz Integrated Circuit Invited International conference

Collaborative Conference on Materials Research 2013  2013.6 

テラヘルツ集積回路に向けたオンチップ伝送線路のモデル化に関する考察 Invited

土谷 亮, 小野寺 秀俊

電子情報通信学会マイクロ波研究会  2013.3  電子情報通信学会

3次元電磁界解析におけるビアのモデル化方法の考察

土谷 亮, 小野寺 秀俊

第31回 シリコンアナログRF研究会, Dec 2012.  2012.12 

Loss Modeling of On-Chip Transmission-Line for Millimeter-Wave and Terahertz Applications Invited International conference

Collaborative Conference on Materials Research 2012  2012.6 

テラヘルツCMOSにおける配線モデル化の課題

第29回シリコンアナログRF研究会  2012.5  電子情報通信学会

Dual-PLL based on Temporal Redundancy for Radiation-Hardening あ

SinNyoung Kim, A. Tsuchiya, H. Onodera

第28回シリコンアナログRF研究会, Mar 2012.  2012.3 

Bandwidth Enhancement for High Speed Amplifier Utilizing Mutually Coupled On-Chip Inductors Invited International conference

2011 International SoC Design Conference  2011.11  IEEK

配線モデル化におけるGrain Boundaryの影響

土谷 亮, 小野寺 秀俊

第27回 シリコンアナログRF研究会, Nov 2011.  2011.11 

100GHzを超える領域での配線損失に関する検討

土谷 亮, 小野寺 秀俊

第26回 シリコンアナログRF研究会, Aug 2011.  2011.8 

異常表皮効果の数値的評価手法

土谷 亮, 小野寺 秀俊

第25回 シリコンアナログRF研究会, May 2011.  2011.5 

Modeling of On-Chip Interconnects for mm-Wave and higher Frequency Application

The 3rd Young Researchers International Symopium  2010.12  GCOE on Photonics and Electronics Science and Engineering

オンチップ配線における異常表皮効果に関する検討

土谷 亮, 小野寺 秀俊

第24回 シリコンアナログRF研究会, Nov 2010.  2010.11 

パネル討論 光と電気は融合可能か? Invited

デザインガイア 2010  2010.11  情報処理学会

ミリ波帯における配線抵抗に関する考察

土谷 亮, 小野寺 秀俊

第23回 シリコンアナログRF研究会, Jul 2010.  2010.7 

複合インダクタを用いたLDドライバの設計

久保木 猛, 大友 祐輔, 土谷 亮, 岸根 桂路, 小野寺 秀俊

第22回シリコンアナログRF研究会, Mar 2010.  2010.5 

ダミーフィルによる伝送損失増加の解析的評価手法

土谷 亮, 小野寺 秀俊

第22回 シリコンアナログRF研究会, Mar 2010.  2010.5 

Transformer peakingにおける解析的設計手法

宮脇 成和, 土谷 亮, 小野寺 秀俊

第22回シリコンアナログRF研究会, Mar 2010.  2010.3 

ダミーフィルを考慮した伝送線路およびスパイラルインダクタの設計 (チュートリアル講演)

土谷 亮, 小野寺 秀俊

第21回 シリコンアナログRF研究会, Nov 2009.  2009.11 

Split-Ring Resonator を用いたチップ内メタ物質の構成に関する検討

土谷 亮, 小野寺 秀俊

第21回 シリコンアナログRF研究会, Nov 2009.  2009.11 

Effect of Dummy Fills on Characteristics of Passive Devices in CMOS Millimeter-Wave Circuits Invited International conference

IEEE 8th International Conference on ASIC  2009.10  IEEE

ダミーフィルがコプレーナ線路の特性に与える影響の位置依存性

土谷 亮, 小野寺 秀俊

第20回 シリコンアナログRF研究会, Jul 2009.  2009.7 

チップ内受動素子のモデリングにおける電磁界解析のノウハウ

土谷 亮, 小野寺 秀俊

第18回 シリコンアナログRF研究会, Dec 2008.  2008.12 

Si-IC におけるダミーフィルを考慮した高周波受動素子のモデル化 Invited

Microwave Workshops and Exhibition 2008  2008.11  電子情報通信学会

ミリ波・準ミリ波帯におけるシリコン上のダミーメタルのスパイラルインダクタへの影響 Invited

アジレント EEsof EDAフォーラム2008  2008.11  アジレントテクノロジー

スパイラルインダクタに対するダミーフィルおよび基板の影響比較

土谷 亮, 小野寺 秀俊

第17回 シリコンアナログRF研究会, Sep 2008.  2008.9 

CMOSミリ波回路におけるオンチップ伝送線路のモデル化 Invited

2008年電子情報通信学会ソサイエティ大会  2008.9  電子情報通信学会

Education Delivery in the Design and Performance of Electrical Packaging and Interconnect Invited International conference

12th IEEE Workshop on Signal Propagation on Interconnects  2008.5  IEEE

スパイラルインダクタ用くし形ダミーフィルの最適形状に関する検討

土谷 亮, 小野寺 秀俊

第16回 シリコンアナログRF研究会, May 2008.  2008.5 

スパイラルインダクタの高周波特性に対する非正方形ダミーフィルの影響評価

土谷 亮, 小野寺 秀俊

第15回 シリコンアナログRF研究会, Feb 2008.  2008.2 

スパイラルインダクタ周辺のダミーフィル挿入最適化の検討

土谷 亮, 小野寺 秀俊

第14回 シリコンアナログRF研究会, Nov 2007.  2007.11 

Modeling of On-Chip Transmission-Lines ---Impact of Orthogonal Wires, Si Substrate and Dummy Fills--- Invited

Microwave Workshops and Exhibition 2007  2007.11  電子情報通信学会

スパイラルインダクタの高周波特性への影響を考慮したダミーフィル挿入方法の検討

土谷 亮, 小野寺 秀俊

第13回 シリコンアナログRF研究会, Sep 2007.  2007.9 

オンチップ差動伝送線路に対する下層配線の影響

久保木 猛, 土谷 亮, 小野寺 秀俊

第16回 シリコンアナログRF研究会, May 2007.  2007.5 

オンチップ配線における配線抵抗変動要因の比較

土谷 亮, 小野寺 秀俊

第11回 シリコンアナログRF研究会, Mar 2007.  2007.3 

シャントコンダクタンスを挿入したオンチップ伝送線路特性評価

Jangsombatsiri Siriporn, 橋本 昌宜, 土谷 亮, 尾上 孝雄

第10回 シリコンアナログRF研究会, Nov 2006.  2006.11 

ダミーフィルが配線特性に与える影響の実測による評価

土谷 亮, 小野寺 秀俊

第10回 シリコンアナログRF研究会, Nov 2006.  2006.11 

0.15um試作PLLのジッタ要因解析

濱田 隆行, 土谷 亮, 小野寺 秀俊

第8回 シリコンアナログRF研究会, May 2006.  2006.5 

ITRS準拠トランジスタモデルとPTMの比較

土谷 亮, 上村 晋一郎, 小野寺 秀俊

第8回 シリコンアナログRF研究会, May 2006.  2006.5 

オンチップ配線の高周波特性に対するダミーメタルの影響

土谷 亮, 小野寺 秀俊

第7回シリコンアナログRF研究会, Feb 2006.  2006.2 

オンチップ配線の特性抽出におけるダミーメタルの影響

土谷 亮, 小野寺 秀俊

第6回シリコンアナログRF研究会  2005.11 

実測と電磁界解析による基板損失の評価

土谷 亮, 橋本 昌宜, 小野寺 秀俊

第3回シリコンアナログRF研究会, Jan 2005.  2005.6 

基板および周辺信号配線が配線特性に及ぼす影響の実測

土谷 亮, 橋本 昌宜, 小野寺 秀俊

第2回シリコンアナログRF研究会, Aug 2004.  2004.8 

オンチップ伝送線路におけるリターン電流評価精度が信号波形に与える影響

土谷 亮, 橋本 昌宜, 小野寺 秀俊

第1回シリコンアナログRF研究会, Apr 2004.  2004.4 

トランスインピーダンスアンプ

中村 誠, 小野寺 秀俊, 土谷 亮

高周波伝送線路

中野 慎介, 野河 正史, 小泉 弘, 土谷 亮, 小野寺 秀俊, 雨貝 太郎

ソレノイドインダクタ

中村 誠, 小野寺 秀俊, 土谷 亮

出力回路および送受信回路

中村 誠, 小野寺 秀俊, 土谷 亮

低損失伝送線路

中野 慎介, 野河 正史, 小泉 弘, 土谷 亮, 小野寺 秀俊

トランスインピーダンスアンプ

中村 誠, 岸根 桂路, 小野寺 秀俊, 土谷 亮

SLDM研究会 優秀論文賞

2002.7   情報処理学会   VLSI 配線の伝送線路化を考慮した駆動力決定手法

土谷 亮, 小野寺 秀俊