Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

This paper proposes a new neighborhood function for the self-organizing map (SOM). As the learning of the SOM progresses, the conventional neighborhood function reduces its magnitude and neighborhood radius, and the learning stops after pre-defined training iterations. On the other hand, the proposed neighborhood function uses only the distance between the weight vector of the winner neuron and the input vector, then the magnitude and radius are computed according to this distance. Since the proposed neighborhood function is not a function of the learning iterations, it allows the SOM to continue its learning without stopping, and it can handle varying input vector distribution. This feature is especially effective under the unknown, dynamically changing input vector space that arises in, e.g., online learning. The proposed function uses vector distance to provide the SOM with voluntary learning capability. Therefore the vector distance plays a role of curiosity of biological brain.

DOI： 10.1109/SSCI.2018.8628891

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

This paper proposes a new scalable hardware SOM architecture in which neurons can easily be increased. Learning of SOM is made of two operations, i.e., winner search and vector update. In the proposed SOM, the winner search is distributed among all neurons. Owing to the distributed winner search circuit, the neuron is modularized and the architecture provides high expandability that makes it easier to increase the neurons. All neurons work in parallel including the winner search, and the proposed SOM processes a single input vector within a single clock cycle. The proposed SOM was implemented in a FPGA, and its performance was examined. Preliminary results of the experiment are presented in this paper.

DOI： 10.1109/IPAS.2018.8708894

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electronics, Information and Communication, Engineers, IEICE  

This paper discusses the effect of pre-grouping on vector classification based on the self-organizing map (SOM). The SOM is an unsupervised learning neural network, and is used to form clusters of vectors using its topology preserving nature. The use of SOMs for practical applications, however, may pose difficulties in achieving high recognition accuracy. For example, in image recognition, the accuracy is degraded due to the variation of lighting conditions. This paper considers the effect of pre-grouping of feature vectors on such types of applications. The proposed pre-grouping functionality is also based on the SOM and introduced into a new parallel configuration of the previously proposed SOM-Hebb classifers. The overall system is implemented and applied to position identification from images obtained in indoor and outdoor settings. The system first performs the grouping of images according to the rough representation of the brightness profile of images, and then assigns each SOM-Hebb classifier in the parallel configuration to one of the groups. Recognition parameters of each classifier are tuned for the vectors belonging to its group. Comparison between the recognition systems with and without the grouping shows that the grouping can improve recognition accuracy.

DOI： 10.1587/transinf.2017EDP7198

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

This paper proposes very unique hardware architecture for self-organizing map (SOM) that is based on frequency modulated (FM) signal. The proposed SOM architecture consists of neurons embedded with winner search and neighborhood function circuits, all of which employ pulse operation. The neuron uses digital frequency-locked loop (DFLL) as its computing element. In terms of modeling the brain in signal level, this approach in the hardware SOM architecture is very significant. The proposed SOM was implemented on FPGA, and its on-chip learning performance was tested by experiments. Preliminary experimental results showed that the proposed hardware SOM was successfully trained to various input vectors, showing topology-preserving nature.

DOI： 10.1109/ISCAS.2018.8351364

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electronics, Information and Communication, Engineers, IEICE  

An FPGA-based hardware hand sign recognition system was proposed in our previous work. The hand sign recognition system consisted of a preprocessing and a self-organizing map (SOM)-Hebb clas- sifier. The training of the SOM-Hebb classifier was carried out by an off-chip computer using training vectors given by the system. The recog- nition performance was reportedly improved by adding perturbation to the training data. The perturbation was added manually during the process of image capture. This paper proposes a new off-chip training method with automatic performance improvement. To improve the system's recognition performance, the off-chip training system adds artificially generated pertur- bation to the training feature vectors. Advantage of the proposed method compared to additive scale perturbation to image is its low computational cost because the number of feature vector elements is much less than that of pixels contained in image. The feasibility of the proposed off-chip training was tested in simulations and experiments using American sign language (ASL). Simulation results showed that the proposed perturbation compu- tation alters the feature vector so that it is same as the one obtained by a scaled image. Experimental results revealed that the proposed off-chip training improved the recognition accuracy from 78.9% to 94.3%.

DOI： 10.1587/transfun.E101.A.499

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This live demonstration shows an FPGA-based real-time hand sign recognition sytem. The system consists of a feature vector extraction and a vector classifier. The SOM-Hebb classifier network is used for the classification network, which is made of a self-organizing map and a feed-forward neural network. Training of the SOM-Hebb classifier is carried out by an off-chip computer. In this demonstration, the hand sign recognition camera is tuned by a newly developed training algorithm for the off-chip learning.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper discusses effect of grouping on vector classifiers that are based on self-organising map (SOM). The SOM is an unsupervised learning neural network, and is used to form clusters using its topology preserving nature. Thus it is used for various pattern recognition applications. In image recognition, recognition accuracy is degraded under difficult lighting conditions. This paper proposes a new image recognition system that employs a grouping method. The proposed system does the grouping of vectors according to their brightness, and multiple vector classifiers are assigned to every groups. Recognition parameters of each classifier are tuned for the vectors belonging to its group. The proposed method is applied to position identification from images obtained from an on-board camera on a mobile robot. Comparison between the recognition systems with and without the grouping shows that the grouping can improve recognition accuracy.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A real-time dynamic hand gesture recognition system with gesture spotting is discussed in this paper. The gesture spotting detects the start and the end of the gesture frames. The system consists of preprocessing, posture sequence generation, and SOM-Hebb network. Feature vectors are computed by the preprocessing from video frames taken by a USB camera in real time, and these feature vectors are fed to the posture sequence generation and a vector that represents the sequence of postures, called a posture sequence vector, is generated. Then, gesture classification and the gesture spotting are performed in the SOM-Hebb network. Our gesture spotting function detects the end of the gesture by using vector distance between the posture sequence vector and the winner neuron's weight vector. The gesture recognition algorithm is implemented on a PC. A USB camera was used to acquire live images. The real time experimental results show that the system recognizes nine gestures with the accuracy of 96.22%.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes a new winner-take-all (WTA) circuit for WTA neural network (WTANN) that is based on frequency modulated signals. WTA finds winner neuron that has the nearest internal weight vector to input vector, and reliable and efficient frequency comparator is required for the implementation of the WTA circuit. This paper proposes a cycle slip detector to estimate frequency difference of the signals. To evaluate the performance of the proposed WTA, VHDL simulation was conducted. Results revealed that accuracy in WTA operation of the proposed method is much better than the previously proposed WTA circuit.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

In previous work, we proposed an FPGA-based hardware hand sign recognition system. A new off-chip learning algorithm for this hardware hand-sign recognition system is described in this paper. The hand-sign system consists of a preprocessing and a SOM-Hebb classifier. The training of the SOM-Hebb classifier is carried out by an off-chip computer using feature vectors given by the recognition system. It was reported that the recognition performance was improved by adding perturbation in the rotation and scaling to the training data for the SOM-Hebb classifier. Since the available training data is in feature vector format, perturbation in the rotation and scaling could not be added during the off-chip learning. Therefore, the perturbation was added during the process of image capture by rotating hand signs or changing the distance between the hand sign and the on-board camera. This paper proposes a new training algorithm for the offchip learning. The algorithm generates training vectors by modifying the feature vector, which is equivalent to adding the scale perturbation in the input image. The feasibility of the system is verified by experiments using 24 patterns of American sign language (ASL). The experimental results show that the proposed algorithm improved the recognition accuracy from 78.5% to 94.3%.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Many self-organizing maps (SOMs) implemented on hardware restrict their neighborhood function values to negative powers of two. In this paper, we propose a novel hardware friendly neighborhood function that is aimed to improve the vector quantization performance of hardware SOM. The quantization performance of the hardware SOM with the proposed neighborhood function is examined by simulations. Simulation results show that the proposed function can improve the hardware SOM's vector quantization capability even though the function value is restricted to negative powers of two. Then, the hardware SOM is implemented on field-programmable gate array to find out the hardware cost and performance speed of the proposed neighborhood function. Experimental results show that the proposed neighborhood function can improve SOM's quantization performance without additional hardware cost or slowing down the operating speed. Due to fully parallel operation, the proposed SOM with 16 x 16 neurons achieves a performance of 25 344 million connections updates per second.

DOI： 10.1109/TNNLS.2015.2398932

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

Neural networks are widely used in various fields due to their superior learning abilities. This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL), and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a global winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the WTA in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning.

DOI： 10.1587/transinf.2014EDP7371

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

It is important to reduce the power consumption of complementary metal oxide semiconductor (CMOS) logic circuits, especially those used in mobile devices. A CMOS logic circuit consists of metal-oxide-semiconductor field-effect transistors (MOSFETs), which consume electrical power dynamically when they charge and discharge load capacitance that is connected to their output. Load capacitance mainly exists in wiring or buses, and transitions between logic 0 and logic 1 cause these charges and discharges. Many methods have been proposed to reduce these transitions. One novel method (called segmentation coding) has recently been proposed that reduces power consumption of CMOS buses carrying band-limited signals, such as audio data. It improves performance by employing dedicated encoders for the upper and lower bits of transmitted data, in which the transition characteristics of band-limited signals are utilized. However, it uses a conventional majority voting circuit in the encoder for lower bits, and the circuit uses many adders to count the number of 1s to calculate the Hamming distance between the transmitted data. This paper proposes segmentation coding with pseudo-majority voting. The proposed pseudo-majority voting circuit counts the number of 1s with fewer circuit resources than the conventional circuit by further utilizing the transition characteristics of band-limited signals. The effectiveness of the proposed method was demonstrated through computer simulations and experiments.

DOI： 10.1587/transele.E98.C.356

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper proposes a hardware posture recognition system with a hybrid network. The hybrid network consists of self-organizing map (SOM) and Hebbian network. Feature vectors are extracted from input posture images, which are mapped to a lower dimensional map of neurons in the SOM. The Hebbian network is a single-layer feedforward neural network trained with a Hebbian learning algorithm to identify categories. The recognition algorithm is robust to the change in location of hand signs, but it is not immune to rotation or scaling. Its robustness to rotation and scaling was improved by adding perturbation to the training data for the SOM-Hebb classifier. In addition, neuron culling is proposed to improve performance. The whole system is implemented on a field-programmable gate array employing novel video processing architecture. The system was designed to recognize 24 American sign language hand signs, and its feasibility was verified through both simulations and experiments. The experimental results revealed that the system could accomplish recognition at a speed of 60 frames/s, while achieving an accuracy of 97.1%. Due to a novel hardware implementation, the circuit size of the proposed system is very small, which is highly suitable for embedded applications.

DOI： 10.1109/TCSVT.2014.2335831

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper proposes a new sine wave approximation method for the PAC of DDFS. Sine wave is approximated by removing the harmonic components from trapezoid waveform. Experimental results show that the proposed PAC is advantageous in the SFDR range less than 60 dBc due to its small hardware cost.

DOI： 10.1587/transfun.E94.A.1581

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper discusses two types of vector classifiers for the hand posture recognition system. One classifier is based on the range check (RC) function, and the other is based on the hybrid network that is made of self-organizing map (SOM) and Hebbian network. In case the learning data and the testing data are different, the system with the hybrid network classifier outperforms the other system in the recognition rate by 9%. Two types of implementations are designed for the RC classifier. One uses parallel architecture and the other employs serial architecture. The size of the RC classifier in serial architecture is 38,000 gate count while the parallel architecture design requires 230,000 gate count. The circuit size of the hybrid network classifier is 606,000 gate count, even though the learning circuit is excluded in the design. The circuit size of the hybrid classifier is almost 2.6 times larger than that of the RC classifier, both use parallel architecture. Compared to the RC classifier in serial architecture, its size is 16 times bigger. Therefore the RC classifier is suitable for the hardware implementation even though the hybrid network classifier provides better performance.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper discusses a hand posture recognition system with a hybrid network classifier. The hybrid network consists of SOM and Hebbian network. Feature vector is extracted from the input hand posture image and the given feature vector is mapped to a lower-dimensional map by the SOM. Then the supervised Hebbian network performs category acquisition and naming. The feasibility of the system is verified by computer simulations. The results show that the recognition performance of the system is quite good if the number of neurons in the SOM is sufficient. Besides the recognition performance, the advantage of the hybrid classifier is the embedded learning capability. It is also expected that the classifier can be extended to recognize dynamic gesture by employing feedback SOM.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：PERGAMON-ELSEVIER SCIENCE LTD  

The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small. (c) 2005 Elsevier Ltd. All rights reserved.

DOI： 10.1016/j.neunet.2005.06.012

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

The self-organizing map (SOM) has found applicability in a wide range of application areas. This paper proposes a new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs). The system uses the DPLL as a computing element because the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. The proposed SOM architecture is described in VHDL and its feasibility is verified by simulation. Results show that the proposed SOM has good quantization capability.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper proposes a new type of digital pulse-mode neuron that employs piecewise-linear function as its activation function. The neuron is implemented on field programmable gate array (FPGA) and tested be experiments. As well as theoretical analysis, the experimental results show that tire piecewise-linear function of the proposed neuron is programmable and robust against the change in the number of input signals. To demonstrate the effect of piecewise-linear activation function, pulse-mode multilayer neural network with on-chip learning is implemented on PPGA with the proposed neuron, and its learning performance is verified by experiments. By approximating tire sigmoid function by the piecewise-linear function, tire convergence rate of the learning and generalization capability are improved.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper describes a new pulse-mode digital neuron which is based on voting neuron. The signal level of the neuron is represented by frequency of pulse signals. The proposed neuron provides adjustable nonlinear function,. which resembles the sigmoid function. The proposed neuron and experimental multilayer neural network (MNN) are implemented on field programmable gate array (FPGA) and various experiments are conducted to test the performance of the proposed system. The experimental results show that the proposed neuron has rigid adjustable nonlinear function.

DOI： 10.1109/TNN.2002.804312

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes a new type of digital pulse mode neuron that employs piecewise linear function as its activation function. Pulse mode multilayer neural network (MNN) with on-chip learning is implemented with the proposed neuron. By approximating the Sigmoid function by the piecewise linear function, the convergence rate of the learning is improved. The proposed MNN is implemented on FPGA and its feasibility is verified by experiments.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：SCRIPTA TECHNICA-JOHN WILEY & SONS  

In this paper, a pulse-mode multilayer neural network with on-chip learning is proposed. The neuron unit uses voting circuit as a nonlinear adder to improve the nonlinear activation function. Moreover, the voting circuit is modified to have adjustable nonlinear characteristic. As the signal level is expressed by the frequency, synapse multipliers are realized by simple frequency converters. The back propagation algorithm is used for the on-chip learning. The proposed multilayer neural network is implemented on field programmable gate array (FPGA), and various experiments are conducted. The results show that the proposed neuron has adjustable nonlinear function. The learning capability of the proposed network is also verified by the experiments. (C) 2000 Scripta Technica.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

This paper describes a new pulse mode hardware multilayer neural network (MNN) that uses floating point number system for synapse weights. Combined with pulse mode operation, the floating point operation is implemented without multiplier. Furthermore, back-propagation algorithm is included in the hardware to provide on-chip learning capability. The proposed MNN is implemented on field programmable gate array (FPGA) and various experiments are conducted to test the performance of the proposed system. The results of the experiments show that the proposed MNN architecture can be used for applications that require high precision in their calculation, and its good on-chip learning capability is also demonstrated.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

A new digital architecture of the frequency-based multilayer neural network (MNN) with on-chip learning is proposed. As the signal level is expressed by the frequency, the multiplier is replaced by a simple frequency converter, and the neuron unit uses the voting circuit as the nonlinear adder to improve the nonlinear characteristic, In addition, the pulse multiplier is employed to enhance the neuron characteristics. The backpropagation algorithm is modified for the on-chip learning, The proposed MNN architecture is implemented on field programmable gate arrays (FPGA's) and the various experiments are conducted to test the performance of the system. The experimental results show that the proposed neuron has a very good nonlinear function owing to the voting circuit. The learning behavior of the MNN with on-chip learning is also tested by experiments, which show that the proposed MNN has good learning and generalization capabilities, Simple and modular structure of the proposed MNN leads to a massive parallel and flexible network architecture, which is well suited for very large scale integration (VLSI) implementation.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

New digital architecture of the frequency-based multilayer neural network (MNN) with on-chip learning is proposed. As the signal level is expressed by the frequency, synaptic multiplier is replaced by a simple frequency converter. Furthermore, the neuron unit uses a voting circuit as the nonlinear adder to have better nonlinear activating function. The back-propagation algorithm is modified for the on-chip learning.
The proposed MNN architecture is implemented on field programmable gate array (FPGA) and the various experiments are conducted to test the performance of the system. The experimental results show that the proposed neuron has a very good nonlinear function owing to the voting circuit. The learning behavior of the proposed MNN is also tested by experiments, which show that the proposed MNN has good learning performance and generalization capabilities.

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Language：English   Publisher：IEEE COMPUTER SOC  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：I E E E  

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Language：Japanese   Publisher：電子情報通信学会通信ソサイエティ  

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Language：Japanese   Publisher：電子情報通信学会通信ソサイエティ  

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Language：Japanese   Publisher：電子情報通信学会  

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Language：Japanese   Publisher：電子通信学会  

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Venue：茨城県つくば市  

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Venue：Naha, Okinawa Japan  

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Venue：Naha, Okinawa Japan  

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Venue：Dallas, Texas, USA  

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Venue：群馬県桐生市  

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Venue：North Taipei, Taiwan  

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Venue：Brisbane, Australia  

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Venue：金沢工業大学  

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Venue：Chiangmai, Thailand  

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Venue：Chiangmai, Thailand  

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Venue：上智大学  

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Venue：上智大学  

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Venue：兵庫県立大学  

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Venue：兵庫県立大学  

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Venue：兵庫県立大学  

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Venue：Anchorage, USA  

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Venue：兵庫県立大学  

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Venue：東京首都大学（東京都）  

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Venue：東京首都大学（東京都）  

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Venue：東京首都大学（東京都）  

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Venue：東京首都大学（東京都）  

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Venue：立命館大学 びわこ・くさつキャンパス（滋賀県草津市）  

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Venue：立命館大学 びわこ・くさつキャンパス（滋賀県草津市）  

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Venue：大阪府立大学（堺市）  

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Venue：Barcelona, Spain  

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Venue：Barcelona, Spain  

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Venue：Paris, France  

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Venue：Atlanta, Georgia  

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Venue：Atlanta, Georgia, USA  

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Venue：Taipei, Taiwan  

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Venue：Auckland, New Zealand  

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