A New Self-Organizing Map with Continuous Learning Capability

Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda

Proceedings of the 2018 IEEE Symposium Series on Computational Intelligence, SSCI 2018   2163 - 2168   2019.1

A New Hardware Self-Organizing Map Architecture with High Expandability

Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda

IEEE 3rd International Conference on Image Processing, Applications and Systems, IPAS 2018   238 - 243   2018.7

A Subspace Newton-Type Method for Approximating Transversely Repelling Chaotic Saddles Reviewed

H. Ito, H. Hikawa, Y. Maeda

IEICE Trans. FUNDAMENTALS   Vol.E101-A, No.7, pp.1127-1131   2018.7

SOM-based vector recognition with pre-grouping functionality

Yuto Kurosaki, Masayoshi Ohta, Hidetaka Ito, Hiroomi Hikawa

IEICE Transactions on Information and Systems   E101D ( 6 )   1657 - 1665   2018.6

Complete mixed-mode oscillation synchronization in weakly coupled nonautonomous Bonhoeffer-van der Pol oscillators Reviewed

N. Inaba, H. Ito, K. Shimizu, H. Hikawa

Progress of Theoretical and Experimental Physics (PTEP)   Volume 2018, Issue 6   2018.6

Hardware Self-Organizing Map Based on Frequency-Modulated Signal and Digital Frequency-Locked Loop

Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda

Proceedings - IEEE International Symposium on Circuits and Systems   2018-   2018.4

Off-chip training with additive perturbation for FPGA-based hand sign recognition system

Hiroomi Hikawa, Masayuki Tamaki, Hidetaka Ito

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E101A ( 2 )   499 - 506   2018.2

Effect of Grouping in Vector Recognition System Based on SOM Reviewed

Masayoshi Ohta, Yuto Kurosaki, Hidetaka Ito, Hiroomi Hikawa

PROCEEDINGS OF 2016 IEEE SYMPOSIUM SERIES ON COMPUTATIONAL INTELLIGENCE (SSCI)   2016

Real Time Gesture Recognition System with Gesture Spotting Function Reviewed

Yuta Ichikawa, Shuji Tashiro, Hidetaka Ito, Hiroomi Hikawa

PROCEEDINGS OF 2016 IEEE SYMPOSIUM SERIES ON COMPUTATIONAL INTELLIGENCE (SSCI)   2016

Improved Winner-Take-All Circuit for Neural Network Based on Frequency-Modulated Signals Reviewed

Hiroomi Hikawa

23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016)   85 - 88   2016

Off-Chip Learning for Hardware Hand-Sign Recognition System Reviewed

Masayuki Tamaki, Hiroomi Hikawa

2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   2575 - 2578   2016

Live Demonstration: Off-Chip Learning for Hardware Hand-Sign Recognition System Reviewed

Masayuki Tamaki, Hiroomi Hikawa

2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   451 - 451   2016

Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function

Hiroomi Hikawa, Yutaka Maeda

IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS   26 ( 11 )   2861 - 2873   2015.11

Scalable Hardware Winner-Take-All Neural Network with DPLL

Masaki Azuma, Hiroomi Hikawa

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E98D ( 10 )   1838 - 1846   2015.10

Low-PowerWiring Method for Band-Limited Signals in CMOS Logic Circuits by Segmentation Coding with Pseudo-Majority Voting

Katsuhiko Ueda, Zuiko Rikuhashi, Kentaro Hayashi, Hiroomi Hikawa

IEICE TRANSACTIONS ON ELECTRONICS   E98C ( 4 )   356 - 363   2015.4

Novel FPGA Implementation of Hand Sign Recognition System With SOM-Hebb Classifier

Hiroomi Hikawa, Keishi Kaida

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY   25 ( 1 )   153 - 166   2015.1

分割符号化により消費電力を低減するCMOS論理回路データ伝送手法 Reviewed

上田勝彦, 陸橋瑞光, 末永美幸, 肥川 宏臣

電子情報通信学会論文誌 C   Vol.J97-C, No.6, pp.249-258   2014.6

Phase-to-Amplitude Converter Based on Accurate Sine Wave Approximation by Trapezoidal Wave Summation Reviewed

HIKAWA Hiroomi, MAEDA Yutaka

The Transactions of the Institute of Electronics, Information and Communication Engineers. A   Vol. J95-A, No.2, pp.813-816 ( 12 )   813 - 816   2012.12

Phase to Amplitude Converter with Optimized Linear Interpolation and Error Compensation ROM Reviewed

NAMBA Taketo, IIDA Takuya, HIKAWA Hiroomi

The IEICE transactions on electronics C   J94-C No.10 pp.337-340 ( 10 )   337 - 340   2011.10

ROM-Less Phase to Amplitude Converter Using Sine Wave Approximation Based on Harmonic Removal from Trapezoid Wave

Hiroomi Hikawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E94A ( 7 )   1581 - 1584   2011.7

Comparison of Range Check Classifier and Hybrid Network Classifier for Hand Sign Recognition System Reviewed

Hiroomi Hikawa, Seito Yamazaki, Tatsuya Ando, Seiji Miyoshi, Yutaka Maeda

2010 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS IJCNN 2010   2010

Handsign Recognition Algorithm for Hardware Implementation Reviewed

HIKAWA Hiroomi, FUJIMURA Hirotada, SATOU Daisuke

The IEICE transactions on information and systems   D, J92-D (3), 405-416 ( 3 )   405 - 416   2009.3

Hand Sign Recognition System Based on Hybrid Network Classifier Reviewed

Yuuki Taki, Hiroomi Hikawa, Seiji Miyoshi, Yutaka Maeda

IJCNN: 2009 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1- 6   1173 - 1180   2009

Hardware Feedback Self-OrganizingMap and Its Application to Mobile Robot Location Identification Reviewed

H. Hikawa, K. Harada, T. Hirabayashi

Journal of Advanced ComputationalIntelligence and Intelligent Informatics   11, (8) 937-945   2007.10

Pattern Classification Algorithm for Hardware Implementation Reviewed

MATSUBARA Shigeki, HIKAWA Hiroomi

The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese edition) A   Vol. J90-A, No.8, 2007年8月, pp.646-654 ( 8 )   646 - 654   2007.8

FPGA implementation of self organizing map with digital phase locked loops

H Hikawa

NEURAL NETWORKS   18 ( 5-6 )   514 - 522   2005.6

A new pulse mode self organizing map hardware with digital phase locked loops Reviewed

H Hikawa

Proceedings of the International Joint Conference on Neural Networks (IJCNN), Vols 1-5   2855 - 2860   2005

Category Recognition System Using Two Ultrasonic Sensors and Combinational Logic Circuit Reviewed

MORITAKE Yusuke, HIKAWA Hiroomi

The Transactions of the Institute of Electronics, Information and Communication Engineers A   Vol. J87-A, No.7, pp.890-898 ( 7 )   890 - 898   2004.7

A digital hardware pulse-mode neuron with plecewise linear activation function

H Hikawa

IEEE TRANSACTIONS ON NEURAL NETWORKS   14 ( 5 )   1028 - 1037   2003.9

A new digital pulse-mode neuron with adjustable activation function

H Hikawa

IEEE TRANSACTIONS ON NEURAL NETWORKS   14 ( 1 )   236 - 242   2003.1

Multilayer Neural Network with Pulse Position Modulation Reviewed

HIKAWA Hiroomi

The Transactions of the Institute of Electronics,Information and Communication Engineers.   Vol. J85-D-II, No.10, pp.1571-1581 ( 10 )   1571 - 1581   2002.10

Hardware Material Recognition System Using Combinatorial Logic Circuit and Ultrasonic Sensor Reviewed

MORITAKE Yuusuke, HIKAWA Hiroomi

The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese edition) A   Vol. J85-A, No.5, pp.610-614 ( 5 )   610 - 614   2002.5

Hardware pulse mode neural netowrk with piecewise linear activation function neurons Reviewed

H Hikawa

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS   524 - 527   2002

Multilayer neural network with on-chip learning based on frequency-modulated pulse signals and voting neurons Reviewed

H Hikawa

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE   84 ( 1 )   32 - 42   2001

Pulse mode multilayer neural network with floating point operation and on-chip learning Reviewed

H Hikawa

IJCNN 2000: PROCEEDINGS OF THE IEEE-INNS-ENNS INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOL II   71 - 76   2000

周波数変調パルスと多数決ニューロンによる学習機能付き多層ニューラルネットワーク Reviewed

肥川宏臣

電子情報通信学会論文誌   Vol. J82-A, No.7, pp.1005-1015 ( 7 )   1005 - 1015   1999.7

Frequency-based multilayer neural network with on-chip learning and enhanced neuron characterisitcs

H Hikawa

IEEE TRANSACTIONS ON NEURAL NETWORKS   10 ( 3 )   545 - 553   1999.5

Implementation of Multilayer Neural Network with Threshold Neurons and its analysis Reviewed

K. Sato, H. Hikawa

Artificial Life and Robotics, Springer   Vol. 3, No. 3,pp.170-175   1999.3

Hardware Efficient Three-Valued Multilayer Neural Network with On-Chip Learning Reviewed

HIKAWA Hiroomi

The Transactions of the Institute of Electronics,Information and Communication Engineers.   Vol. J81-D-II, No.12, pp.2811-2818 ( 12 )   2811 - 2818   1998.12

Interference Cancellation with Interpolated FFT Reviewed

H. Hikawa, V. K. Jain

Vol. E81-A, No.6,pp.1105-1112   1998.7

Multilayer Neural Network with Threshold Neurons Reviewed

H. Hikawa, K. Sato

Vol. E81-A, No.6,pp.1105-1112   1998.7

Learning performance of frequency-modulation digital neural network with on-chip learning Reviewed

H Hikawa

IEEE WORLD CONGRESS ON COMPUTATIONAL INTELLIGENCE   557 - 562   1998

AN ARCHITECTURE FOR WSI RAPID PROTOTYPING

VK JAIN, H HIKAWA, DC KEEZER

COMPUTER   25 ( 4 )   71 - 75   1992.4

A Radix-8 Wafer Scale FFT Processor Reviewed

E. E. Swartzlander, V. K. Jain, H. Hikawa

Journal of VLSI Signal Processing   Vol.4,pp.165-176   1992.1

ENHANCED DIGITAL FREQUENCY-SYNTHESIZER AND ITS ANALYSIS Reviewed

H HIKAWA, S MORI, VK JAIN

1990 IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS, VOLS 1-4   628 - 631   1990

HIGH-PERFORMANCE DIGITAL FREQUENCY-SYNTHESIZER Reviewed

H HIKAWA, S MORI, VK JAIN

IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS : ICC 90, VOLS 1-4   1423 - 1427   1990

適応型２値量子化位相周波数比較器によるＤＰＬＬの特性改善 Reviewed

中島収, 肥川宏臣, 井上貴史, 森真作

電子情報通信学会論文誌   Vol.J72-B-1, No.7, pp.609-616 ( 7 )   p609 - 616   1989.7

ノッチ周波数特性を持つＤＰＬＬを用いた干渉波抑圧 Reviewed

井上貴史, 肥川宏臣, 森新作

電子情報通信学会論文誌   Vol.J72-B-1, No.7, pp.601-608 ( 7 )   p601 - 608   1989.7

A Digital Frequency Synthesizer with a Phase Accumulator Reviewed

H. Hikawa, S. Mori

Vol.E72, No.6,pp.719-726   1989.6

Performance Improvement of All Digital Phase-Locked Loop with Adaptive Multilevel-Quantized Phase Comparator Reviewed

O. Nakajima, H. Hikawa, S. Mori

Trans. IEICE Japan   Vol.E72, No.3,pp.194-201   194 - 201   1989.3

A Digital Phase-Locked Loop with a Low Frequency Clock Reviewed

H. Hikawa, S. Mori

Vol.E72, No.2,pp.111-117   1989.2

INTERFERENCE SUPPRESSION USING DPLL WITH NOTCH FREQUENCY CHARACTERISTIC Reviewed

T INOUE, H HIKAWA, S MORI

1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3   2084 - 2087   1989

ディジタル位相同期ループを用いた網同期構成に関する研究 Reviewed

浅野健志, 肥川宏臣, 森真作

電子情報通信学会論文誌   Vol.J71-B, No.2, pp.150-155 ( 2 )   p150 - 155   1988.2

広帯域ディジタル位相同期ループ Reviewed

肥川宏臣, 鄭南寧, 森真作

電子情報通信学会論文誌   Vol.J69-B, No.2, pp.154-160 ( 2 )   p154 - 160   1986.2

A New Hardware Self-Organizing Map Architecture with High Expandability

H. Hikawa, H. Ito, Y. Maeda

Third IEEE International Conference on Image Processing, Applications and Systems (IPAS 2018)  2018.12 

A New Self-Organizing Map with Continuous Learning Capability

H. Hikawa, H. Ito, Y. Maeda

Proc. 2018 IEEE Symposium Series on Computational Intelligence (SSCI2018)  2018.11 

拡張性が高いハードウェア自己組織化マップ

肥川 宏臣

2018.10 

周波数同期ループを用いたハードウェアSOM

肥川 宏臣

2018.6 

Hardware Self-Organizing Map Based on Frequency-Modulated Signal and Digital Frequency-Locked Loop

H. Hikawa, H. Ito, Y. Maeda

Proc. 2018 IEEE International Symposium on Circuits and Systems (ISCAS2018)  2018.5 

周波数変調パルスを用いたハードウェア自己組織化マップ

肥川 宏臣, 伊藤 秀隆

信学技報  2018.1 

Continuous Learning of the SOM with an Adaptive Neighborhood Function

YOSHIMI, Hikari, HIKAWA, Hiroomi, ITO, Hidetaka

Proc. 2017 International Symposium on Nonlinear Theory and Its Applications (NOLTA2017)  2017.12 

A Numerical Method for Designing Periodic Orbits Embedded in Chaotic Attractors

ITO, Hidetaka, HIKAWA, Hiroomi, MAEDA, Yutaka

Proc. 2017 International Symposium on Nonlinear Theory and Its Applications (NOLTA2017)  2017.12 

Winner-Take-All Neural Network with Distributed Winner Search Circuit

HANADA, Kazuki, UEDA, Shoya, ITO, Hidetaka, HIKAWA, Hiroomi

Proc. 2017 International Symposium on Nonlinear Theory and Its Applications (NOLTA2017)  2017.12 

適応型近傍関数を用いた自己組織化マップの学習特性

吉見 光, 伊藤 秀隆, 肥川 宏臣

信学技報  2017.10 

自己組織化マップを利用したリアルタイムジェスチャ認識システム

市川 雄太, 伊藤 秀隆, 肥川 宏臣

電子情報通信学会技術研究報告, 機能情報システム研究会  2017.10 

Effect of Grouping in Vector Recognition System Based on SOM

OHTA Masayoshi, KUROSAKI Yuto, ITO Hidetaka, HIKAWA Hiroomi

Proc. 2016 IEEE Symposium Series on Computational Intelligence (IEEE SSCI 2016)  2016.12 

Real Time Gesture Recognition System with Gesture Spotting Function

ICHIKAWA Yuta, TASHIRO Shuji, ITO Hidetaka, HIKAWA Hiroomi

Proc. 2016 IEEE Symposium Series on Computational Intelligence (IEEE SSCI 2016)  2016.12 

Improved Winner-Take-All Circuit for Neural Network Based on Frequency-Modulated Signals

HIKAWA Hiroomi

Proc. 23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS 2016)  2016.12 

Gesture Spotting by Using Vector Distance of Self-Organizing Map

ICHIKAWA Yuta, TASHIRO Shuji, ITO Hidetaka, HIKAWA Hiroomi

Proc. 23rd International Conference on Neural Information Processing (ICONIP 2016)  2016.10 

Off-chip learning for hardware hand-sign recognition system

TAMAKI Masayuki, HIKAWA,Hiroomi

Proc. 2016 IEEE International Symposium on Circuits and Systems (IEEE ISCAS 2016)  2016.5 

Live demonstration: Off-chip learning for hardware hand-sign recognition system

TAMAKI Masayuki, HIKAWA Hiroomi

Proc. 2016 IEEE International Symposium on Circuits and Systems (IEEE ISCAS 2016)  2016.5 

Vector Classification by a Winner-Take-All Neural Network with Digital Frequency-Locked Loop

HIKAWA Hiroomi

Proc. 2015 IEEE International Joint Conference on Neural Networks (IEEE IJCNN 2015)  2015.7 

Winner-Take-All Neural Network with Digital Frequency-Locked Loop

HIKAWA Hiroomi

Proc. 2015 IEEE International Symposium on Circuits and Systems (IEEE ISCAS 2015)  2015.5 

Supervised Learning of DPLL Based Winner-Take-All Neural Network

AZUMA Masaki, HIKAWA Hiroomi

Proc. 2014 IEEE Symposium Series on Computational Intelligence (SSCI 2014)  2014.12 

Low-power Wiring Method in CMOS Logics Circuits by Segmentation Coding and Pseudo Majority Voting

UEDA Katsuhiko, RIKUHASHI Zuiko, HAYASHI Kentaro, HIKAWA Hiroomi

Proc. 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014)  2014.6 

グレイコードによるCMOS 論理回路の消費電力削減

林 健太郎, 渕上 直人, 上田 勝彦, 肥川 宏臣

電子情報通信学会 機能集積システム研究会  2014.3 

A new Winner-Take-All Neural Network Using DPLL and Phase Modulated Signal

M. Azuma, H. Hikawa

2013 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2013)  2013.11 

Color-Space Image Compression with Hardware Self-Organizing Map

N. Terahara, Y. Oba, H. Hikawa

2013 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2013)  2013.11 

DPLL Based Hardware SOM with A New Winner-Take-All Circuit

Hiroomi Hikawa

The International Joint Conference on Neural Network 2013  2013.8 

位相変調信号と DPLL を用いた Winner-Take-All ニューラルネットワークの検討

東 正樹, 肥川 宏臣

電子情報通信学会 機能集積システム研究会  2013.7 

指文字認識システムのハードウェア実装

戒田圭司, 大橋俊介, 肥川宏臣

電子情報通信学会, 機能情報システム研究会  2013.3 

分割符号化手法によるCMOS 論理回路の配線消費電力削減

陸橋瑞光, 末永美幸, 上田勝彦, 肥川宏臣

電子情報通信学会, 機能情報システム研究会  2013.3 

学習ピクセル入力をランダム化したハードウェアSOMを用いた色量子化システム

田原大樹, 肥川宏臣

平成24年電気関係学会関西支部連合大会  2012.12 

ハードウェア自己組織化マップにおける近傍関数の改良

林健太郎, 山本洸太, 陸橋瑞光, 肥川宏臣

平成24年電気関係学会関西支部連合大会  2012.12 

自己組織化マップとフィードバック付き Hebb 学習ネットワークを用いたジェスチャ認識システム

荒賀雄介, 肥川宏臣

平成24年電気関係学会関西支部連合大会  2012.12 

CMOS論理回路での配線消費電力低減の一手法

上田勝彦, 陸橋瑞光, 肥川宏臣

平成24年電気関係学会関西支部連合大会  2012.12 

Sequential Vector Classifier Based on SOM and Feedback Hebbian Network

Y. Araga, Z. Rikuhashi, H. Hikawa

2012 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2012)  2012.11 

学習ピクセル入力のランダム化による速度改善を行ったハードウェアSOM を用いた色量子化システム

田原大樹, 肥川宏臣

電子情報通信学会, 機能情報システム研究会  2012.10 

指文字認識システムの特徴抽出回路のハードウェア設計

戒田圭司, 肥川宏臣

電子情報通信学会, 機能情報システム研究会  2012.10 

ハードウェア自己組織化マップにおける近傍関数の改良

林健太郎, 山本洸太, 陸橋瑞光, 肥川宏臣

電子情報通信学会, 機能情報システム研究会  2012.6 

台形波の高調波除去に基づく正弦波近似回路

肥川宏臣

電子情報通信学会, 機能情報システム研究会  2012.6 

Real Time Gesture Recognition System Using Posture Classifier and Jordan Recurrent Neural Network

Y. Araga, M. Shirabayashi, K. Kaida, H. Hikawa

WCCI 2012 IEEE World Congress on Computational Intelligence  2012.6 

特徴ベクトルの正規化を用いた大きさ変化にロバストな指文字認識システム

山崎生人 (D), 安藤達也 (D), 肥川宏臣 (D)

電子情報通信学会 機能情報システム研究会  2012.3 

Automatic Generation of Hardware Self-Organizing Map For FPGA implementation

K. Yamamoto (D), H. Hikawa

2011 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (IEEE ISPACS 2011)  2011.12 

Hardware Design of a Color Quantization with Self-Organizing Map

Y. Oba, H. Hikawa

2011 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (IEEE ISPACS 2011)  2011.12 

シストリックアレイニューラルネットワークのVHDL 記述の自動生成

陸橋瑞光 (D), 肥川宏臣

電子情報通信学会 機能情報システム研究会  2011.11 

ハードウェア自己組織化マップを用いた色量子化システム

大場義郎 (D), 山本洸太 (D), 肥川宏臣

電子情報通信学会 機能情報システム研究会  2011.11 

自己組織化マップを用いた色量子化システムのハードウェア設計

大場義郎 (D), 山本洸太 (D), 長井貴裕 (D), 肥川宏臣

平成23年電気関係学会関西支部連合大会  2011.10 

階層型ネットワークを用いたリアルタイム指文字認識システム

戒田圭司 (D), 肥川宏臣

平成23年電気関係学会関西支部連合大会  2011.10 

ポスチャ認識とJordan型リカレントニューラルネットワークを用いたジェスチャ認識システム

荒賀雄介 (D), 肥川宏臣

平成23年電気関係学会関西支部連合大会  2011.10 

Hand Sign Recognition System Based on SOM-Hebb Hybrid Network

H. Hikawa, K. Kaida (D)

2011 IEEE International Conference on Systems, Man, and Cybernetics (IEEE SMC 2011)  2011.10 

回路並列性が調節可能な自己組織化マップのVHDLコードの自動生成

山本洸太 (D), 大場義郎(D), 陸端瑞光 (D), 肥川宏臣

平成23年電気関係学会関西支部連合大会  2011.10 

Study on Gesture Recognition System Using Posture Classifier and Jordan Recurrent Neural Network

HIKAWA,Hiroomi

Proc. of 2011 International Joint Conference on Neural Networks (IJCNN2011)  2011.7 

自己組織化マップを用いた画像圧縮システムのFPGA実装

堂元健司 (D), 肥川宏臣

電子情報通信学会2011年総合大会  2011.3 

最適化した線形近似回路と補正ROMを用いたPAC

難波健人 (D), 飯田卓哉 (D), 肥川宏臣

電子情報通信学会2011年総合大会  2011.3 

フレームに含まれるポスチャ認識結果を用いた絞り込み手法によるジェスチャ認識

田村史郎 (D), 肥川宏臣

電子情報通信学会2011年総合大会  2011.3 

構成変更が容易なハードウェアSOMアーキテクチャ

岡崎友佑 (D), 大場義郎 (D), 山本洸太 (D), 堀 哲郎 (B), 肥川宏臣

電子情報通信学会2011年総合大会  2011.3 

指文字認識システムにおけるレンジチェックネットワークと階層化ネットワークの性能比較

山崎生人 (D), 安藤達也 (D), 瀧勇輝 (D), 田村史郎 (D), 肥川宏臣

平成22年電気関係学会関西連合大会  2010.11 

柔軟性を考慮したハードウェア自己組織化マップアーキテクチャ

大場義郎 (D), 山本洸太 (D), 岡崎友佑 (D), 肥川宏臣

平成22年電気関係学会関西連合大会  2010.11 

線形近似と補正ROMを用いた位相振幅変換回路

飯田卓哉 (D), 難波健人 (D), 肥川宏臣

電子情報通信学会2010ソサイエティ大会  2010.9 

Comparison of Range Check Classifier and Hybrid Network Classifier for Hand Sign Recognition System

H. Hikawa, S. Yamazaki (D), T. Ando (D), S. Miyoshi, Y. Maeda

2010 IEEE World Congress on Computational Intelligence (WCCI 2010)  2010.7 

Image Compression with Hardware Self-Organizing Map

H. Hikawa, K. Doumoto (D), S. Miyoshi, Y. Maeda

2010 IEEE World Congress on Computational Intelligence (WCCI 2010)  2010.7 

Phase Amplitude Converter with Conditional Shift Operation

H. Hikawa, T. Namba (D)

2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010)  2010.5 

On Automatic Generation of VHDL Code for Self-Organizing Map

A. Onoo, H. Hikawa, S. Miyoshi, Y. Maeda

2009 International Joint Conference on Neural Networks (INNS-IEEE IJCNN 2009)  2009.6 

Hand Sign Recognition System Based on Hybrid Network Classifier

Y. Taki (D), H. Hikawa, S. Miyoshi, Y. Maeda

2009 International Joint Conference on Neural Networks (INNS-IEEE IJCNN 2009)  2009.6 

DDFS with New Sinusoid Approximation Based on Harmonics Removal

H. Hikawa

2009 IEEE International Symposium on Circuits and Systems (ISCAS 2009)  2009.5 

大きさの変化にロバストな指文字認識システム

佐藤大輔, 肥川宏臣

機能集積回路研究会  2009.3 

自己組織化マップハードウェアの自動生成について

小野尾 彰, 肥川宏臣

ニューロコンピューティング研究会  2008.11 

Hardware design of Japanese Hand Sign Recognition System

H. Hikawa, H. Fujimura

15th International Conference, ICONIP 2008  2008.11 

Simplified DFT for Hand Posture Recognition System

H. Hikawa

Proceedings of 2008 International Symposium on Nonlinear Theory and itsApplications (NOLTA 2008)  2008.9 

全方位カメラを用いた位置認識システムの特性評価

釘宮香織, 今村仁美

2008.9 

A New Hardware Friendly Vector Distance Evaluation Function for Vector Classifiers

H. Hikawa

Springer  2007.11 

Japanese Hand Sign Recognition System

H. Fujimura, Y. Sakai, H. Hikawa

2007 International Conference on Neural Information Processing  2007.11 

A New Hardware Friendly Vector Distance Evaluation Functionfor Vector Classifiers

H. Hikawa

2007 International Conference on Neural Information Processing  2007.11